A primer on memory consistency and cache coherence

著者

• Sorin, Daniel J.
• Hill, Mark D.
• Wood, David A.

書誌事項

A primer on memory consistency and cache coherence

Daniel J. Sorin, Mark D. Hill, and David A. Wood

（Synthesis lectures on computer architecture, 16）

Morgan & Claypool, c2011

• : pbk

注記

Includes bibliographical references

内容説明・目次

内容説明

Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems.

目次

Preface Introduction to Consistency and Coherence Coherence Basics Memory Consistency Motivation and Sequential Consistency Total Store Order and the x86 Memory Model Relaxed Memory Consistency Coherence Protocols Snooping Coherence Protocols Directory Coherence Protocols Advanced Topics in Coherence Author Biographies

「Nielsen BookData」 より

詳細情報

• NII書誌ID(NCID): BB09969369
• ISBN:
  • 9781608455645
• 出版国コード: xx
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: [s.l.]
• ページ数/冊数: xiii, 195 p.
• 大きさ: 24 cm
• 親書誌ID:
  • BB05535017