Time-to-digital converters
著者
書誌事項
Time-to-digital converters
（Advanced microelectronics, 29）
Springer, c2010
大学図書館所蔵 全7件
注記
Includes bibliographical references and index
内容説明・目次
内容説明
Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.
目次
List of Symbols and Abreviations. 1 Foreword. 2 Time-to-Digital Converter Basics. 2.1 Motivation - The Way to the Time Domain. 2.2 Analog Time-to-Digital Converters - The First Generation. 2.3 Fully Digital TDCs - The Second Generation. 2.4 Basic Digital Delay-Line Based TDC. 2.5 Synchronous vs. Asynchronous Time Interval Measurement. 3 Theory of TDC Operation. 3.1 Basic Performance Figures. 3.2 Quantization Error Revisited. 3.3 Non-Linear Imperfections of TDC Characteristic. 3.4 Dynamic Performance and Effective Resolution. 3.5 Timing Figures. 3.6 Noise Shaping in Time-to-Digital Converters. 3.7 Process Variations in TDCs. 4 Advanced TDC Design Issues. 4.1 Bipolar Time-to-Digital Converter. 4.2 Looped Time-to-Digital Converter. 4.3 Linearly Extended TDC Loop. 4.4 Delay-Locked-Loop Based TDC. 4.5 Hierarchical Time-to-Digital Converter. 4.6 Multi-Event Time-to-Digital Converter. 4.7 On-Chip Test and Characterization Engine. 4.8 Time Domain Quantizer. 4.9 Summary TDC Architectures. 5 Time-to-Digital Converters with Sub-Gatedelay Resolution - The Third Generation. 5.1 Sub-Gate Delay Resolution. 5.2 Parallel Scaled Delay Elements. 5.3 Vernier TDC. 5.4 Pulse-Shrinking TDC. 5.5 Local Passive Interpolation TDC. 5.6 Gated Ring Oscillator TDC. 5.7 Time-to-Digital Converter with Time Amplification. 6 Applications for Time-to-Digital Converters. 6.1 Digital Phase Locked Loop. 6.2 TDC based Analog-to-Digital Converter. References. Index.
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