Technology and applications of 3D integrated circuits

著者

• Garrou, Philip
• Bower, Christopher
• Ramm, Peter

書誌事項

Technology and applications of 3D integrated circuits

edited by Philip Garrou, Christopher Bower and Peter Ramm

（Handbook of 3D integration, v. 1-2）

Wiley-VCH, c2012

• : pbk

注記

Originally published in 2 separate vols. in 2008

Includes bibliographical references and index

内容説明・目次

内容説明

The first encompassing treatise of this new and very important field puts the known physical limitations for classic 2D microelectronics into perspective with the requirements for further microelectronics developments and market necessities. This two-volume handbook presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging technology, and thermal aspects. It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration to the semiconductor roadmap of the industry. Before going on to cover processing technology and 3D structure fabrication strategies in detail. This is followed by fields of application and a look at the future of 3D integration. The editors have assembled contributions from key academic and industrial players in the field, including Intel, Micron, IBM, Infineon, Qimonda, NXP, Philips, Toshiba, Semitool, EVG, Tezzaron, Lincoln Labs, Fraunhofer, RPI, IMEC, CEA-LETI and many others.

目次

Volume 1 PREFACE INTRODUCTION TO 3D INTEGRATION Introduction Historical Evolution of Stacked Wafer Concepts 3D Packaging vs 3D Integration Non-TSV 3D Stacking Technologies DRIVERS FOR 3D INTEGRATION Introduction Electrical Performance Power Consumption and Noise Form Factor Lower Cost Application Based Drivers OVERVIEW OF 3D INTEGRATION PROCESS TECHNOLOGY 3D Integration Terminology Processing Sequences Technologies for 3D Integration PART I: Through Silicon Via Fabrication DEEP REACTIVE ION ETCHING OF THROUGH SILICON VIAS Introduction DRIE Equipment and Characterization DRIE Processing Practical Solutions in Via Etching Concluding Remarks LASER ABLATION Introduction Laser Technology for 3D Packaging For Si Substrate Results for 3D Chip Stacking Reliabilities The Future SIO2 Introduction Dielectric CVD Dielectric Film Properties 3D-Specifics Regarding SiO2 Dielectrics Concluding Remarks INSULATION - ORGANIC DIELECTRICS Parylene Plasma-Polymerized BCB Spray-Coated Organic Insulators Laser-Drilled Organics Concluding Remarks COPPER PLATING Introduction Copper Plating Equipment Copper Plating Processes Factors Affecting Copper Plating Plating Chemistries Plating Process Requirements Summary METALLIZATION BY CHEMICAL VAPOR DEPOSITION OF W AND CU Introduction Commercial Precursors Deposition Process Flow Complete TSV Metallization Including Filling and Etchback/CMP Conclusions PART II: Wafer Thinning and Bonding Technology FABRICATION, PROCESSING AND SINGULATION OF THIN WAFERS Applications for Thin Silicon Dies Principal Facts: Thinning and Wafer Bow Grinding and Thinning Stability and Flexibility Chip Thickness, Theoretical Model, Macroscopic Features Stabilizing the Thin Wafer: Tapes and Carrier Systems Separating the Chips: Dicing Influencing the Stability Conclusions Summary OVERVIEW OF BONDING TECHNOLOGIES FOR 3D INTEGRATION Introduction Direct Bonding Adhesive and Solder Bonding Comparison of the Different Bonding Technologies CHIP-TO-WAFER AND WAFER-TO-WAFER INTEGRATION SCHEMES Decision Criteria for 3D Integration Enabling Technologies Integration Schemes for 3D Interconnect Conclusion POLYMER ADHESIVE BONDING TECHNOLOGY Polymer Adhesive Bonding Principle Polymer Adhesive Bonding Requirements and Materials Wafer Bonding Technology Using Polymer Adhesives Bonding Characterizations Conclusions BONDING WITH INTERMETALLIC COMPOUNDS Introduction Technological Concepts Conclusion Volume 2 PART III: Integration Processes COMMERCIAL ACTIVITY Introduction Chip-on-Chip Activity Imaging Chips with TSV Memory Microprocessors & Misc. Applications WAFER-LEVEL 3D SYSTEM INTEGRATION Introduction Wafer-Level 3D System Integration Technologies Reliability Issues Conclusions INTERCONNECT PROCESS AT THE UNIVERSITY OF ARKANSAS Introduction TSV Process Flow Chip Assembly System Integration Summary VERTICAL INTERCONNECTION BY ASET Introduction Fabrication Process Overview Via Filling by Cu Electrodeposition Handling of Thin Wafer 3D Chip Stacking Thermal Performance of Chip Stack Module Electric Performance of Vertical Interconnection Practical Application of Through-vias Conclusion 3D INTEGRATION AT CEA-LETI Introduction Circuit Transfer for Efficient Stacking in 3D Integration Non-Destructive Characterization of Stacked Layers Example of 3D Integration Application Developments Summary LINCOLN LABORATORY.S 3D CIRCUIT INTEGRATION TECHNOLOGY Introduction Lincoln Laboratory.s Wafer-Scale 3D Circuit Integration Technology Transferred FDSOI Transistor and Device Properties 3D Circuit and Device Results Summary 3D INTEGRATION TECHNOLOGIES AT IMEC Introduction 413 Key Requirements for 3D-Interconnect Technologies 3D Technologies at IMEC FABRICATION USING COPPER THERMO-COMPRESSION BONDING AT MIT Introduction Copper Thermo-Compression Bonding Process Flow Discussion Summary RENSSELAER 3D INTEGRATION PROCESSES Introduction Via-Last 3D Platform Using Adhesive Wafer Bonding and Cu Damascene Inter-Wafer Interconnect Via-Last 3D Platform Feasibility Demonstration: Via-Chain Structure with Key Unit Processes of Alignment, Bonding, Thinning andInter-wafer Interconnection Via-First 3D Platform with Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers Via-First 3D Platform Feasibility Demonstration: Via-Chain Structure with Cu/BCB Redistribution Layers Unit Process Advancements Carbon Nanotube (CNT) Interconnect Summary 3D INTEGRATION AT TEZZARON SEMICONDUCTOR CORPORATION Introduction Copper Bonding Yield Issues Interconnect Density Process Requirements for 3D DRAM FaStack Process Overview Bonding Before Thinning Tezzaron.s TSVs Stacking Process Flow Details (with SuperContacts) Stacking Process Flow with SuperVias Additional Stacking Process Issues Working 3D Devices Qualification Results FaStack Summary Abbreviations and Definitions 3D INTEGRATION AT ZIPTRONIX, INC. Introduction Direct Bonding Direct Bond Interconnect Process Cost and Supply Chain Considerations 3D INTEGRATION ZYCUBE Introduction Current 3D-LSI - New CSP Device for Sensors Future 3D-LSI Technology PART IV: Design, Performance, and Thermal Management DESIGN FOR 3D INTEGRATION AT NORTH CAROLINA STATE UNIVERSITY Why 3D? Interconnect-Driven Case Studies Computer-Aided Design Discussion MODELING APPROACHES AND DESIGN METHODS FOR 3D SYSTEM DESIGN Introduction Modeling and Simulation Design Methods for 3D Integration Conclusions MULTIPROJECT CIRCUIT DESIGN AND LAYOUT IN LINCOLN LABORATORY.S 3D TECHNOLOGY Introduction 3D Design and Layout Practice Design and Submission Procedures COMPUTER-AIDED DESIGN FOR 3D CIRCUITS AT THE UNIVERSITY OF MINNESOTA Introduction Thermal Analysis of 3D Designs Thermally-Driven Placement and Routing of 3D Designs Power Grid Design in 3D Conclusion ELECTRICAL PERFORMANCE OF 3D CIRCUITS Introduction 3D Chip Stack Technology Electrical Performance of 3D Contacts Summary and Conclusion TESTING OF 3D CIRCUITS Introduction Yield and 3D Integration Known Good Die (KGD) Wafer Stacking Versus Die Stacking Defect Tolerant and Fault Tolerant 3D Stacks THERMAL MANAGEMENT OF VERTICALLY INTEGRATED PACKAGES Introduction Fundamentals of Heat Transfer Thermal-Packaging Modeling Metrology in Thermal Packaging Thermal Packaging Components Heat Removal in Vertically-Integrated Packages PART V: Applications 3D AND MICROPROCESSORS Introduction Design of 3D Microprocessor Systems Fabrication of 3D Microprocessor Systems Conclusions 3D MEMORIES Introduction Applications Redistribution Layer Through Wafer Interconnect Stacking Additional Issues Future of 3D Memories 3D READ-OUT INTEGRATED CIRCUITS FOR ADVANCED SENSOR ARRAYS Introduction Current Activity in 3D ROICs Conclusions POWER DEVICES Introduction Wafer Level Packaging for Discrete Semiconductor Devices Packaging for PowerMOSFET Devices Chip Size Packaging of Vertical MOSFETs Metal TWI Process for Vertical MOSFETs Further Evaluation of the TWI MOSFET CSPs Outlook WIRELESS SENSOR SYSTEMS - THE E-CUBES PROJECT Introduction e-CUBES Concept Enabling 3D Integration Technologies e-CUBES GHz Radios e-CUBES Applications and Roadmap Conclusions

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詳細情報

• NII書誌ID(NCID): BB11103458
• ISBN:
  • 9783527332656
• 出版国コード: gw
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Weinheim
• ページ数/冊数: xxvi, 773 p.
• 大きさ: 24 cm
• 分類:
  • DC23 : 621.3815
• 件名:
  • LCSH : Integrated circuits
  • LCSH : Integrated circuits -- Design and construction
  • LCSH : Semiconductor wafers
  • LCSH : Three -- dimensional imaging
• 親書誌ID:
  • BB18909233