Design-for-test and test optimization techniques for TSV-based 3D stacked ICs
Author(s)
Bibliographic Information
Design-for-test and test optimization techniques for TSV-based 3D stacked ICs
Springer, c2014
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Includes bibliographical references
Description and Table of Contents
Description
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Table of Contents
Introduction.- Wafer Stacking and 3D Memory Test.- Built-in Self-Test for TSVs.- Pre-Bond TSV Test Through TSV Probing.- Pre-Bond TSV Test Through TSV Probing.- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.- Post-Bond Test Wrappers and Emerging Test Standards.- Test-Architecture Optimization and Test Scheduling.- Conclusions.
by "Nielsen BookData"