Logic synthesis and verification
著者
書誌事項
Logic synthesis and verification
Springer Science+Business Media, 2002
- : softcover
大学図書館所蔵 全1件
  青森
  岩手
  宮城
  秋田
  山形
  福島
  茨城
  栃木
  群馬
  埼玉
  千葉
  東京
  神奈川
  新潟
  富山
  石川
  福井
  山梨
  長野
  岐阜
  静岡
  愛知
  三重
  滋賀
  京都
  大阪
  兵庫
  奈良
  和歌山
  鳥取
  島根
  岡山
  広島
  山口
  徳島
  香川
  愛媛
  高知
  福岡
  佐賀
  長崎
  熊本
  大分
  宮崎
  鹿児島
  沖縄
  韓国
  中国
  タイ
  イギリス
  ドイツ
  スイス
  フランス
  ベルギー
  オランダ
  スウェーデン
  ノルウェー
  アメリカ
注記
consulting editor: Robert K. Brayton
"Originally published by Kluwer Academic in 2002" -- T.p. verso
"Softcover reprint of the hardcover 1st edition 2002" -- T.p. verso
Includes bibliographical references and index
内容説明・目次
内容説明
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges.
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
目次
- Foreword. Preface. 1: Two-Level Logic Minimization
- O. Coudert, T. Sasao. 2: Multi-Level Logic Optimization
- M. Fujita, Y. Matsunaga, M. Ciesielski. 3: Flexibility in Logic
- E. Sentovich, D. Brand. 4: Multiple-Valued Logic Synthesis and Optimization
- E. Dubrovna. 5: Technology Mapping
- L. Stok, V. Tiwari. 6: Technology-based Transformations
- R. Murgai. 7: Logical and Physical Design: A Flow Perspective
- O. Coudert. 8: Logic Synthesis for Low Power
- L. Benini, G. de Micheli. 9: Optimization of Synchronous Circuits
- S. Hassoun, T. Villa. 10: Asynchronous Control Circuits
- L. Lavagno, S.M. Nowick. 11: Ordered Binary Decision Diagrams
- R.E. Bryant, C. Meinel. 12: SAT and ATPG: Algorithms for Boolean Decision Problems
- W. Kunz, J. Marques-Silva, S. Malik. 13: Combinatorial and Sequential Equivalence Checking
- A. Kuehlmann, C.A.J. van Eijk. 14: Static Timing Analysis
- Y. Kukimoto, M. Berkelaar, K. Sakallah. 15: The Future of Logic Synthesis and Verification
- R.K. Brayton. Appendices: A: About the Authors. B: Author Contact Information. Index.
「Nielsen BookData」 より