A primer on hardware prefetching

Author(s)
Bibliographic Information

A primer on hardware prefetching

Babak Falsafi, Thomas F. Wenisch

(Synthesis lectures on computer architecture, 28)

Morgan & Claypool, c2014

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Note

Includes bibliographical references (p. 41-[52])

Description and Table of Contents

Description

Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the "Memory Wall." To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching-predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses-is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.

Table of Contents

Preface Introduction Instruction Prefetching Data Prefetching Concluding Remarks Bibliography Author Biographies

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Details
  • NCID
    BB25708606
  • ISBN
    • 9781608459520
  • Country Code
    xx
  • Title Language Code
    eng
  • Text Language Code
    eng
  • Place of Publication
    [S.l.]
  • Pages/Volumes
    xiv, 53 p.
  • Size
    24 cm
  • Parent Bibliography ID
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