Hardware IP security and trust

著者

    • Mishra, Prabhat
    • Bhunia, Swarup
    • Tehranipoor, Mohammad H.

書誌事項

Hardware IP security and trust

Prabhat Mishra, Swarup Bhunia, Mark Tehranipoor, editors

Springer, c2017

大学図書館所蔵 件 / 3

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注記

Includes bibliographical references and index

内容説明・目次

内容説明

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

目次

Part I. Introduction.- Chapter 1.Security and Trust Vulnerabilities in Third-party IPs.- PArt II.Trust Analysis.- Chapter 2.Security Rule Check.- Chapter 3.Digital Circuit Vulnerabilities to Hardware Trojans.- Chapter 4.Code Coverage Analysis for IP Trust Verification.- Chapter 5.Analyzing Circuit Layout to Probing Attack.- Chapter 6.Testing of Side Channel Leakage of Cryptographic IPs: Metrics and Evaluations.- Part III.- Effective Countermeasures.- Chapter 7.Hardware Hardening Approaches using Camouflaging, Encryption and Obfuscation.- Chapter 8.A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Passive Side Channel Attacks.- Part IV.- Chapter 9.Validation of IP Security and Trust.- Chapter 10.IP Trust Validation using Proof-carrying Hardware.- Chapter 11. Hardware Trust Verification.- Chapter 12.Verification of Unspecified IP Functionality.- Chapter 13.Verifying Security Properties in Modern SoCs using Instruction-level Abstractions.- Chapter 14. Test Generation for Detection of Malicious Parametric Variations.- Part V. Conclusions.- Chapter 15.The Future of Trustworthy SoC Design.

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