Transaction processing on modern hardware

著者

• Sadoghi, Mohammad
• Blanas, Spyros

書誌事項

Transaction processing on modern hardware

Mohammad Sadoghi, Spyros Blanas

（Synthesis lectures on data management, #58）

Morgan & Claypool, c2019

• : pbk

注記

Includes bibliographical references (p. 105-119)

DOI:10.2200/S00896ED1V01Y201901DTM058

内容説明・目次

内容説明

The last decade has brought groundbreaking developments in transaction processing. This resurgence of an otherwise mature research area has spurred from the diminishing cost per GB of DRAM that allows many transaction processing workloads to be entirely memory-resident. This shift demanded a pause to fundamentally rethink the architecture of database systems. The data storage lexicon has now expanded beyond spinning disks and RAID levels to include the cache hierarchy, memory consistency models, cache coherence and write invalidation costs, NUMA regions, and coherence domains. New memory technologies promise fast non-volatile storage and expose unchartered trade-offs for transactional durability, such as exploiting byte-addressable hot and cold storage through persistent programming that promotes simpler recovery protocols. In the meantime, the plateauing single-threaded processor performance has brought massive concurrency within a single node, first in the form of multi-core, and now with many-core and heterogeneous processors. The exciting possibility to reshape the storage, transaction, logging, and recovery layers of next-generation systems on emerging hardware have prompted the database research community to vigorously debate the trade-offs between specialized kernels that narrowly focus on transaction processing performance vs. designs that permit transactionally consistent data accesses from decision support and analytical workloads. In this book, we aim to classify and distill the new body of work on transaction processing that has surfaced in the last decade to navigate researchers and practitioners through this intricate research subject.

目次

Introduction Transaction Concepts Multi-Version Concurrency Revisited Coordination-Avoidance Concurrency Novel Transactional System Architectures Hardware Assisted Transactional Utilities Transactions on Heterogeneous Hardware Outlook: The Era of Hardware Specialization and Beyond Bibliography Authors' Biographies

「Nielsen BookData」 より

詳細情報

• NII書誌ID(NCID): BB28390638
• ISBN:
  • 9781681734996
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: [San Rafael, Calif.]
• ページ数/冊数: xv, 122 p.
• 大きさ: 24 cm
• 親書誌ID:
  • BB02626080