A formal, hierarchical design and validation methodology for VLSI

Author(s)

• Davie, Bruce S.

Bibliographic Information

A formal, hierarchical design and validation methodology for VLSI

Bruce S. Davie

University of Edinburgh, Department of Computer Science, 1988

Note

Includes bibliography (p. 225-234)

Author's thesis (Ph.D.)--University of Edinbungh, 1988

CST-55-88

Details

• NCID: BC08580693
• Country Code: uk
• Title Language Code: eng
• Text Language Code: eng
• Place of Publication: Edinburgh
• Pages/Volumes: vi, 234 p.
• Size: 21 cm