Power-efficient network-on-chips : design and evaluation
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書誌事項
Power-efficient network-on-chips : design and evaluation
（Advances in computers, v. 124）
Academic Press, 2022
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注記
Includes bibliographical references
内容説明・目次
内容説明
Advances in Computers, Volume 124 presents updates on innovations in computer hardware, software, theory, design and applications, with this updated volume including new chapters on Traffic-Load-Aware Virtual Channel Power-gating in Network-on-Chips, An Efficient DVS Scheme for On-chip Networks, A Power-Performance Balanced Network-on-Chip for Mixed CPU-GPU Systems, Routerless Networks-on-Chip, Routing Algorithm Design for Power- and Temperature-Aware NoCs, Approximate Communication for Energy-Efficient Network-on-Chip, Power-Efficient NoC Design by Partial Topology Reconfiguration, The Design of a Deflection-based Energy-efficient On-chip Network, and Power-Gating in Networks-on-Chip.
目次
Preface Ali R. Hurson 1. Traffic-Load-Aware Virtual Channel Power-gating in Network-on-Chips Hamid Sarbazi-Azad 2. An Efficient DVS Scheme for On-chip Networks Hamid Sarbazi-Azad 3. A Power-Performance Balanced Network-on-Chip for Mixed CPU-GPU Systems Hamid Sarbazi-Azad 4. Routerless Networks-on-Chip Bella Bose and Fawaz Alazemi 5. Routing Algorithm Design for Power- and Temperature-Aware NoCs Masoumeh Ebrahimi and Kun-Chih (Jimmy) Chen 6. Approximate Communication for Energy-Efficient Network-on-Chip Ling Wang 7. Power-Efficient NoC Design by Partial Topology Reconfiguration Mehdi Modarressi 8. The Design of a Deflection-based Energy-efficient On-chip Network Onur Mutlu and Rachata Ausavarungnirun 9. Power-Gating in Networks-on-Chip Shaahin Hessabi
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