Digital logic : with an introduction to Verilog and FPGA-based design

著者

書誌事項

Digital logic : with an introduction to Verilog and FPGA-based design

M. Rafiquzzaman, Steven A. McNinch

John Wiley & Sons, c2020

  • : pbk

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注記

Includes bibliographical references (p. 437-438) and index

内容説明・目次

内容説明

DIGITAL LOGIC

目次

Preface ix 1 Introduction to Digital Systems 1 1.1 Explanation of Terms 2 1.2 Design Levels 4 1.3 Combinational vs. Sequential Systems 4 1.4 Digital Circuits 5 1.4.1 Diodes 5 1.4.2 Transistors 5 1.4.3 MOS Transistors 11 1.5 Integrated Circuits (ICs) 14 1.6 CAD (Computer-Aided Design) 16 1.7 Evolution of Digital Logic, Microprocessors, and Microcontrollers 16 1.8 A Typical Application of a Digital System such as a Microcontroller 18 2 Number Systems, Arithmetic/Logic Operations, and Codes 21 2.1 Number Systems 21 2.1.1 General Number Representation 21 2.1.2 Converting Numbers from One Base to Another 23 2.2 Unsigned and Signed Binary Numbers 27 2.3 Codes 30 2.3.1 Binary-Coded-Decimal Code (8421 Code) 30 2.3.2 Alphanumeric Codes 31 2.3.3 Excess-3 Code 31 2.3.4 Gray Code 33 2.3.5 Unicode 35 2.4 Fixed-Point and Floating-Point Representations 35 2.5 Arithmetic Operations 36 2.5.1 Binary Arithmetic 36 2.5.2 BCD Arithmetic 44 2.5.3 Multiword Binary Addition and Subtraction 45 2.5.4 Binary Multiplication and Division by Shift Operations 46 2.6 Error Correction and Detection 48 Questions and Problems 50 3 Digital Logic Gates, Boolean Algebra, and Simplification 53 3.1 Basic Logic Operations 53 3.1.1 NOT Operation 53 3.1.2 OR operation 54 3.1.3 AND operation 56 3.2 Other Logic Operations 57 3.2.1 NOR operation 57 3.2.2 NAND operation 58 3.2.3 Exclusive-OR operation (XOR) 59 3.2.4 Exclusive-NOR Operation (XNOR) 61 3.3 Positive and Negative Logic 62 3.4 Boolean Algebra 63 3.4.1 Boolean Identities 64 3.4.2 Simplification Using Boolean Identities 65 3.4.3 Consensus Theorem 69 3.4.4 Getting Rid of Glitches or Hazards in Combinational Circuits 70 3.4.5 Complement of a Boolean Function 71 3.5 XOR / XNOR Implementations 71 Questions and Problems 74 4 Minterms, Maxterms, and Karnaugh Map 77 4.1 Standard Representations 77 4.2 Karnaugh Maps 81 4.2.1 Two-Variable K-map 81 4.2.2 Three-Variable K-map 82 4.2.3 Four-Variable K-map 84 4.2.4 Prime Implicants 87 4.2.5 Expressing a Boolean function in Product-of-sums (POS) form using a K-map 89 4.2.6 Don't Care Conditions 90 4.2.7 Five-Variable K-map 94 4.3 Quine-McCluskey Method 95 4.4 Implementation of Digital Circuits with NAND, and NOR Gates 96 4.4.1 NAND Gate Implementation 97 4.4.2 NOR Gate Implementation 98 Questions and Problems 103 5 Analysis and Design of Combinational Circuits Using Gates 107 5.1 Basic Concepts 107 5.2 Analysis of a Combinational Logic Circuit 107 5.3 Design of Combinational Circuits Using Logic Gates 108 5.4 Multiple-Output Combinational Circuits 113 Questions and Problems 118 6 Design of Typical Combinational Logic Components 121 6.1 Design of Typical Combinational Logic Components 121 6.2 Comparators 121 6.3 Decoders 124 6.4 Encoders 130 6.5 Multiplexers 133 6.6 Demultiplexers 137 6.7 Binary Adder/Subtractor and BCD Adder 139 Questions and Problems 148 7 Combinational Shifter, Fast Adders, Array Multipliers, ALU, & PLDS 151 7.1 Combinational Shifter 151 7.2 Central Processing Unit (CPU) 152 7.3 Arithmetic Logic Unit (ALU) 154 7.4 Read-Only Memories (ROMs) 165 7.5 Programmable Logic Devices (PLDs) 167 7.6 Commercially Available Field Programmable Devices (FPDs) 170 Questions and Problems 172 8 Combinational Logic Using Verilog 175 8.1 Hardware Description Languages (HDLs) 175 8.2 Basics of Verilog 176 8.2.1 Verilog keywords 176 8.2.2 Representing numbers in Verilog 176 8.2.3 A typical Verilog Segment 177 8.3 Structural Modeling 182 8.4 Dataflow Modeling 189 8.5 Behavioral modeling 195 8.5.1 if-else block 197 8.5.2 Modeling logical conditions in a circuit 198 8.5.3 Case-endcase construct 198 8.5.4 Conditional Operator 200 8.6 Simulation 201 Questions and Problems 207 9 Latches and Flip-Flops 211 9.1 Latches and Flip-Flops 211 9.1.1 SR Latch 211 9.1.2 Gated SR Latch 213 9.1.3 Gated D Latch 213 9.1.4 Edge-Trigerred D Flip-Flop 214 9.1.5 JK Flip-Flop 216 9.1.6 T Flip-Flop 217 9.2 Timing parameters for edge-triggered flip-flops 218 9.3 Preset and Clear Inputs 219 9.4 Summary of Flip-Flops 220 Questions and Problems 224 10 Analysis and Design of Sequential Circuits 227 10.1 Introduction 227 10.2 Analysis of Synchronous Sequential Circuits 228 10.3 Types of Synchronous Sequential Circuits 233 10.4 Minimization of States 235 10.5 Design of Synchronous Sequential Circuits 237 10.6 Serial Adder 240 10.7 Sequence Generator/Detector 242 10.8 Random-Access Memory (RAM) 245 10.9 Algorithmic State Machines (ASM) Chart 247 10.10 Asynchronous Sequential Circuits 255 Questions and Problems 258 11 Counters and Registers 263 11.1 Design of Counters 263 11.2 Design of Registers 268 11.2.1 Shift Register 268 11.2.2 "Shift register" Counters 271 11.2.3 General-Purpose Register (GPR) 275 Questions and Problems 277 12 Sequential Logic Design Using Verilog 281 12.1 Basics 281 12.2 Examples Illustrating Non-blocking and Blocking Assignments 283 12.3 RTL (Register Transfer Level) modeling 289 Questions and Problems 298 13 Implementation of Digital Design Using FPGA 301 13.1 Basics of FPGA 301 13.1.1 LUTs (Look-Up Tables) 302 13.1.2 Programmable Switch Matrix 308 13.1.3 Configurable Logic Blocks (CLBs) 308 13.1.4 FPGA Architecture 311 13.1.5 FPGA Programming 311 13.2 A Typical FPGA Chip 312 13.2.1 Configuration Pins 314 13.2.2 User I/O Pins 315 13.2.3 Power/Ground Pins 315 13.3 A Typical FPGA Board 315 13.4 FPGA-based Design and Implementation 320 13.4.1 Design 320 13.4.2 Synthesis 320 13.4.3 Implementation, Programming, and Verification 320 13.5 FPGA Examples 322 Questions and Problems 374 Appendix A: Answers to Selected Problems 379 Appendix B: Glossary 389 Appendix C: Step-By-Step Tutorial for Downloading and Installing Xilinx Vivado IDE 395 Appendix D: Step-By-Step Tutorial for Creating & Simulating a Verilog Design Using Xilinx Vivado IDE 399 I Combinational Circuit 399 II Sequential Circuit 407 Appendix E: Step-By-Step Procedure for Implementing FPGA-Based Design Using Vivado IDE & Nexys A7 FPGA Board 419 I Combinational Circuit 419 II FPGA Implementation of Sequential Circuit 426 Bibliography 437 Index 439

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