A pipelined multi-core machine with operating system support : hardware implementation and correctness proof
Author(s)
Bibliographic Information
A pipelined multi-core machine with operating system support : hardware implementation and correctness proof
（Lecture notes in computer science, 9999 . LNCS sublibrary ; SL 1 . Theoretical computer science and general issues）
Springer, c2020
- : pbk
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Note
Includes bibliographical references (p. [627]-628)
Description and Table of Contents
Description
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Muller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
* MIPS instruction set architecture (ISA) for application and for system programming
* cache coherent memory system
* store buffers in front of the data caches
* interrupts and exceptions
* memory management units (MMUs)
* pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
* local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
* I/O-interrupt controller and a disk
Table of Contents
Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.
by "Nielsen BookData"
