RTL modeling with SystemVerilog for simulation and synthesis : using SystemVerilog for ASIC and FPGA design

Author(s)

• Sutherland, Stuart

Bibliographic Information

RTL modeling with SystemVerilog for simulation and synthesis : using SystemVerilog for ASIC and FPGA design

Stuart Sutherland

Sutherland HDL, c2017

• : [pbk.]

Note

Includes bibliographical references and index

• NCID: BD04448829
• ISBN:
  • 9781546776345
• Country Code: us
• Title Language Code: eng
• Text Language Code: eng
• Place of Publication: Tualatin, Or.
• Pages/Volumes: xxxi, 453 p.
• Size: 23 cm
• Subject Headings:
  • LCSH : Verilog (Computer hardware description language)
  • LCSH : Electronic digital computers -- Design and construction
  • LCSH : Computer simulation