RTL modeling with SystemVerilog for simulation and synthesis : using SystemVerilog for ASIC and FPGA design

著者

• Sutherland, Stuart

書誌事項

RTL modeling with SystemVerilog for simulation and synthesis : using SystemVerilog for ASIC and FPGA design

Stuart Sutherland

Sutherland HDL, c2017

• : [pbk.]

注記

Includes bibliographical references and index

詳細情報

• NII書誌ID(NCID): BD04448829
• ISBN:
  • 9781546776345
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Tualatin, Or.
• ページ数/冊数: xxxi, 453 p.
• 大きさ: 23 cm
• 件名:
  • LCSH : Verilog (Computer hardware description language)
  • LCSH : Electronic digital computers -- Design and construction
  • LCSH : Computer simulation