横山 新 YOKOYAMA Shin

Articles:  21-40 of 42

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  • Estimation of Nitrogen Ion Energy in Sterilization Technology by Plasma Based Ion Implantation  [in Japanese]

    KONDOU Youhei , NAKASHIMA Takeru , TANAKA Takeshi , TAKAGI Toshinori , WATANABE Satoshi , OHKURA Kensaku , SHIBAHARA Kentaro , YOKOYAMA Shin

    Plasma based ion implantation (PBII) with negative voltage pulses to the test specimen has been applied to the sterilization process as a technique suitable for three-dimensional work pieces. Pulsed h …

    Shinku 48(5), 339-342, 2005-05-20

    J-STAGE  References (7)

  • Influence of Wafer Storage Environment on MOS Device Characteristics  [in Japanese]

    YOKOYAMA Shin , YOSHINO Takenobu , FUJII Toshiaki , SHIBAHARA Kentaro , NAKAJIMA Anri , KIKKAWA Takamaro , SUNAMI Hideo , KHOSRU Quazi D. M.

    The influence of wafer storage environment on oxidation and organic contamination of Si surfaces has been investigated. And the electronic reliability of thin (2.8 nm) SiO<SUB>2</SUB> film …

    Earozoru Kenkyu 17(2), 96-104, 2002-06-20

    J-STAGE  References (28)

  • Atomic-layer-deposited silicon-nitride/SiO_2 stacked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors  [in Japanese]

    YOSHIMOTO Takashi , KIDERA Toshirou , KHOSRU Quazi D. M. , NAKAJIMA Anri , YOKOYAMA Shin

    An extremely thin (≤0.4nm) sillcon-niteride layer has been deposited on tthermally grown SiO_2 by an atomic-layer-deposition (ALD) technique. The boron penetration through the stacked gate dielectr …

    Technical report of IEICE. SDM 101(107), 37-41, 2001-05-31

    References (13)

  • Influence of Organic Contamination on Hot-Electron Degradation of Thin Thermal Silicon Dioxides  [in Japanese]

    YOKOYAMA Shin , SHIBAHARA Kentaro , NAKAJIMA Anri , KIKKAWA Takamaro , SUNAMI Hideo , KHOSRU Quazi D. M. , YOSHINO Takenobu

    For the n-channel MOS transistor with the gate oxide of 〜3 nm thick, the influence of the organic contamination before and after the gate oxidation on hot-clectron degradation of the oxide was investi …

    Technical report of IEICE. SDM 101(107), 19-24, 2001-05-31

    References (14)

  • Ultra Clean Technology Using UV/Photoelectron Method for Semiconductor Transportation and Its Effect on MOS Devices  [in Japanese]

    YOSHINO Takenobu , YOKOYAMA Shin , FUJII Toshiaki , SUZUKI Tsukuru

    Feasibility of a plastic wafer box with a UV/photoelectron cleaning unit (UV unit) for a practical application has been investigated. Chemical contaminant evaluations for the box air and Si wafer surf …

    Earozoru Kenkyu 16(1), 57-64, 2001-03-20

    J-STAGE  References (16)

  • 光と電子が作るアメニティ--人,食品,ウエハに対する快適環境  [in Japanese]

    藤井 敏昭 , 坂本 和彦 , 横山 新 [他]

    Ebara engineering review. (186), 13-18, 2000-01

  • 3K1045 Super cleaning of mini-environments  [in Japanese]

    Fujii T. , Yokoyama S. , Sakamoto K.

    大気環境学会年会講演要旨集 (41), 540, 2000

    NDL Digital Collections 

  • Super Cleaning of Closed Space by UV/photoelectron Method Using Photocatalyst  [in Japanese]

    FUJII Toshiaki , SUZUKI Tsukuru , SAKAMOTO Kazuhiko , YOKOYAMA Shin , HIROSE Masataka

    A new super cleaning equipment of a closed space using a photocatalyst (TiO<SUB>2</SUB>) in a UV/photoelectron method was developed. The newly developed equipment has photocatalyst between …

    Earozoru Kenkyu 13(2), 110-118, 1998-06-20

    J-STAGE  References (21) Cited by (3)

  • Electrical Conduction of Double-Barrier Ultrasmall MOS Transistors  [in Japanese]

    HATANO Tsuyoshi , NOMURA Akihiro , YOSHIDA Masayoshi , NAKAJIMA Anri , SHIBAHARA Kentaro , YOKOYAMA Shin

    Novel ultrasmall MOS transistors with double potential barriers are proposed.The structure is similar to the LDD (Lightly Doped Drain) MOS transistors with two gates.The double potential barriers are …

    Technical report of IEICE. SDM 98(30), 15-19, 1998-04-23

    References (8)

  • Electrical Conduction of Double-Barrier Ultrasmall MOS Transistors  [in Japanese]

    HATANO Tsuyoshi , NOMURA Akihiro , YOSHIDA Masayoshi , NAKAJIMA Anri , SHIBAHARA Kentaro , YOKOYAMA Shin

    Novel ultrasmall MOS transistors with double potential barriers are proposed. The structure is similar to the LDD (Lightly Doped Drain) MOS transitors with two gates. The double potential barriers are …

    IEICE technical report. Electron devices 98(28), 15-19, 1998-04-23

    References (8)

  • Evaluation of Wafer Material Dependence on LOCOS Edge Defects  [in Japanese]

    KAWAKAMI Nobuyuki , AOKI Yasuyuki , KUGIMIYA Toshihiro , SHIBAHARA Kentaro , YOKOYAMA Shin

    The wafer material dependence on defect generation during deep submicron LOCOS process was evaluated using four types of Czochralski wafer. The correlation between the dislocation density and the oxyg …

    Technical report of IEICE. SDM 97(446), 87-93, 1997-12-12

    References (8)

  • Pattern Matching Circuit Using Optical Bus Lines  [in Japanese]

    Doi Takeshi , Uehara Akihito , Takahashi Yoshiyuki , Yokoyama Shin , Iwata Atsushi , Hirose Masataka

    光インターコネクションはMCMやWSIの金属配線による問題を解決するアーキテクチャとして期待されている。我々は、光インタコネクションの応用例として、パターン認識システムを採り上げ、システムを高速化することを目指して研究を進めている。今回、パターン認識システムで入力パターンの分配及びパターンの距離比較演算用の光バスとして用いる、双方向に伝搬可能な導波路を設計した。また、この光バスでwired-ORに …

    Proceedings of the Society Conference of IEICE 1997年.エレクトロニクス(2), 84, 1997-08-13

  • Problems in Ultra Shallow Junction Formartion forsub 0.1μm MOSFETs  [in Japanese]

    Shibahara Kentaro , Mifuji Michihiko , Yokoyama Shin , Hirose Masataka

    MOSFET縮小のための課題は多くあるが浅い接合の形成はその中でも基本的且つ重要なものである。本論ではn-MOSFETの微細化のためのn^+-p接合形関しての述べる。サブ0.1μm 級のn-MOSFETのため接合形成法としては最も一般的なAsのイオン注入法とPSGからの固相拡散による方法があげられる。またAsよりも質量が大きく, 拡散係数が小さいことから浅い接合形成に有利と考えられるSbの注入も試 …

    Proceedings of the IEICE General Conference 1997年.エレクトロニクス(2), 331-332, 1997-03-06

  • 光結合集積回路製作技術  [in Japanese]

    横山 新

    FEDジャ-ナル 7(2), 22-31, 1997-02

  • Removal of Fine Particle by UV/Photoelectron Method under Low Pressure Condition  [in Japanese]

    FUJII Toshiaki , OKUYAMA Kikuo , YOKOYAMA Shin , HIROSE Masataka

    空気清浄 34(1), 11-16, 1996-05-31

    References (13)

  • DESIGN AND FABRICATION OF OPTICALLY INTERCONNECTED PATTERN RECOGNITION SYSTEM  [in Japanese]

    DOI TAKESHI , NAMBA TOHRU , UEHARA AKIHITO , NAGATA MAKOTO , MIYAZAKI SEIICHI , SHIBAHARA KENTARO , YOKOYAMA SHIN , IWATA ATSUSHI , AE TADASHI , HIROSE MASATAKA

    The test chip of optical interconnected pattern recognition system was designed and fabricated. For optical waveguides on Si VLSI chips, compact size and high transmission efficiency are required. To …

    Technical report of IEICE. ICD 95(427), 9-14, 1995-12-15

    References (8)

  • Atomic Layer Controlled Deposition of Silicon-Nitride with Self-Limiting Mechanism  [in Japanese]

    GOTO Hiroshi , SHIBAHARA Kentaro , YOKOYAMA Shin

    We have succeeded in growing thin (2-10 nm) silicon-nitride (SiN) film by atomic layer deposition (ALD) with half-molecular-layer (ML) of self-limiting mechanism. The SiN film has been deposited by re …

    Technical report of IEICE. SDM 95(399), 47-54, 1995-12-07

    References (14)

  • New Memory LSI′s with Very High Data Transfer Speed Using Optical Interconnection  [in Japanese]

    Koyanagi Mitsumasa , Abara Reiji , Miyake Kohji , Yokoyama Shin

    Recently,the performance of microprocessor has been significantly improved.However,the access speed of DRAM which is used as a main memory has been hardly improved.As a result,the difference of the op …

    Technical report of IEICE. SDM 93(349), 45-53, 1993-11-26

  • Evaluation of Arsenic Implanted Ultra-Shallow n^+/p Junction by Medium Energy Ion Scattering  [in Japanese]

    Yokoyama Shin , Zbigniew J. Radzimski , Watanabe Takeshi , Ishibashi Kensaku , Hirose Masataka

    Ultra-shallow(〜24nm),low-leakage current(area component=6.3x10^-11>A, cm^2,peripheral component=3.8x10^-12>A/cm)n^+/p junction has been fabricated by low-energy(10keV)and low-temperature(-130℃) …

    Technical report of IEICE. SDM 93(191), 1-8, 1993-08-23

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