中澤 喜三郎 Nakazawa Kisaburo

ID:1000090217696

明星大学情報学部電子情報学科 Department of Electronics and Computer Science, Meisei University (1999年 CiNii収録論文より)

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Articles:  1-20 of 51

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  • Performance Analysis of Multistage Interconnection Network for Massively Parallel Processors  [in Japanese]

    MISHIMA Takeshi , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    In this paper, we propose a new method for theoretical performance analysis of multi-stage interconnection network, based on a probability model. In several researches on that class of network so far, …

    Transactions of Information Processing Society of Japan 40(5), 1985-1995, 1999-05-15

    IPSJ  IR  References (13)

  • Performance Evaluation of NPB Kernel CG on CP - PACS (Special Issue on Parallel Processings)  [in Japanese]

    ITAKURA Kenichi , MATSUBARA Masazumi , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    We evaluate the performance massively parallel processor CP-PACS on NAS Parallel Benchmarks Kernel CG. Since Kernel CG requires global data transfer and short vector processing, it is hard to achieve …

    Transactions of Information Processing Society of Japan 39(6), 1757-1765, 1998-06-15

    IPSJ  IR  References (13) Cited by (3)

  • Performance Evaluation of CP-PACS' Interconnection Network  [in Japanese]

    MATSUBARA MASAZUMI , ITAKURA KEN'ICHI , BOKU TAISUKE , NAKAMURA HIROSHI , NAKAZAWA KISABURO

    CP-PACS, a massively parallel processor, is equipped with the 3-dimensional Hyper-Crossbar Network as an interconnection network and introduces a fast data transfer protocol named Remote-DMA transfer. …

    IPSJ SIG Notes 67, 55-60, 1997-08-19

    References (6) Cited by (2)

  • Evaluation of the basic performance of CP-PACS  [in Japanese]

    ITAKURA KEN'ICHI , ABEI YOSHITO , MATSUBARA MASAZUMI , BOKU TAISUKE , NAKAMURA HIROSHI , NAKAZAWA KISABURO

    The massively parallel processor CP-PACS has two special features', PVP-SW (Pseudo Vector Processor based on Slide Window) for tolerating memory access latency and 3 dimentional Hyper-Crossbar Network …

    IPSJ SIG Notes 123, 19-24, 1997-03-06

    References (10) Cited by (3)

  • Design Assistance for Advanced Processors Using Hardware Description Language AIDL  [in Japanese]

    MORIMOTO Takayuki , SAITO Kazushi , NAKAMURA Hiroshi , BOKU Taisuke , NAKAZAWA Kisaburo

    In order to design advanced processors best suited for design purposes in a short time, designers have to simulate their designs to select best suited architectures and implementations in the wide var …

    IPSJ SIG Notes 121, 57-63, 1996-12-12

    References (13) Cited by (3)

  • Design of Router Chip for Hyper-Crossbar Network Using VHDL  [in Japanese]

    MURAKAMI Yoshiki , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    Hyper-Crossbar Network provides very high performance and large flexibility as an interconnection network for massively parallel processors. Up to the present, performance with two routing algorithms …

    IPSJ SIG Notes 121, 17-24, 1996-12-12

    References (6)

  • Fast List Vector Computation on Pseudo Vector Processor  [in Japanese]

    HIRONO Akira , NAKAMURA Hiroshi , BOKU Taisuke , NAKAZAWA Kisaburo

    In large scientific/engineering applications, data caches do not work effectively because of little temporal locality. We have proposed "Pseudo Vector Processor based on Slide-Windowed Registers (PVP- …

    Transactions of Information Processing Society of Japan 37(10), 1850-1858, 1996-10-15

    IPSJ  IR  References (9) Cited by (1)

  • Performance evaluation CP-PACS on CG benchmark  [in Japanese]

    ITAKURA KEN'ICHI , BOKU TAISUKE , NAKAMURA HIROSHI , NAKAZAWA KISABURO

    In this research, we evaluate NAS Parallel Benchmarks Kernel CG on massively Parallel processor CP-PACS, and analyze the result. CP-PACS's CPU has a special register which is auto-incremented by clock …

    IPSJ SIG Notes 63, 31-36, 1996-10-04

    References (9) Cited by (2)

  • VIPPES : A Performance Pre-Evaluation System for Parallel Processors  [in Japanese]

    MISHIMA MASAHIRO , ITAKURA KEN'ICHI , BOKU TAISUKE , NAKAMURA HIROSHI , NAKAZAWA KISABURO

    In this paper, we propose and implement a performance pre-evaluation system for parallel processors, named VIPPES (VIrtual Parallel Processor Evaluation System). In this system, we analyze the behavio …

    IPSJ SIG Notes 62, 27-32, 1996-08-28

    References (6) Cited by (1)

  • Implementation PVM on CP-PACS  [in Japanese]

    MATSUBARA MASAZUMI , HATTORI MASAKI , ITAKURA KEN'ICHI , BOKU TAISUKE , NAKAMURA HIROSHI , NAKAZAWA KISABURO

    In this reseach, we implement PVM on CP-PACS. CP-PACS, a massively parallel processor, is aimed to resolve large scale scientific problems. In order to get high-performance, we efficiently use the hig …

    IPSJ SIG Notes 119, 13-18, 1996-08-27

    References (5) Cited by (1)

  • Adaptive Routing by Dynamic Selection of Virtual Channels on Hyper - Crossbar Network  [in Japanese]

    SONE Takeshi , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    In this paper, we show that routing schemes on inter-processor communicating network can be classified into four types depending on the usage of virtual channel and routing algorithm. We evaluate the …

    Transactions of Information Processing Society of Japan 37(7), 1409-1418, 1996-07-15

    IPSJ  IR  References (12) Cited by (2)

  • LINPACK Benchmark Evaluation on CP-PACS Pilot-Model  [in Japanese]

    SONE Takeshi , HATTORI Masaki , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    In this study, we evaluate the actual performance of the prototype of CP-PACS named PILOT-1. CP-PACS, a massively parallel processor, is aimed to solve large scale scientific problems. PILOT-1 is a pa …

    IPSJ SIG Notes 117, 83-88, 1996-03-05

    References (7) Cited by (1)

  • The Architecture of Massively Parallel Processor CP-PACS  [in Japanese]

    NAKAZAWA Kisaburo , NAKAMURA Hiroshi , BOKU Taisuke

    IPSJ Magazine 37(1), 18-28, 1996-01-15

    IPSJ  IR  References (21) Cited by (13)

  • CP-PACS : A massively parallel computer system for computational physics  [in Japanese]

    Nakazawa Kisaburo

    The outline of CP-PACS, a massively parallel computer system (MIMD, distributed memory type) for research of computational physics, is presented. The development of CP-PACS, started in April 1992, aim …

    Bulletin of the Japan Society for Industrial and Applied Mathematics 6(1), 17-28, 1996

    J-STAGE  References (12)

  • Performance Evaluation of the Pseudo Vector Processor in List Vector Computation  [in Japanese]

    廣野 哲 , 森本 貴之 , 中村 宏 , 朴 泰祐 , 中澤 喜三郎

    大規模科学技術計算の分野では、データ領域が非常に大きく、データの時間的局所性が少ない。そのためスカラプロセッサではデータキャッシュが有効に働かず、主記憶アクセスペナルティのために性能が著しく低下する。この問題に対処するため、我々は浮動小数点レジスタをスライドウィンドウ化した擬似ベクトルプロセッサPVP-SW(Pseudo Vector Processor based on Slide-Window …

    全国大会講演論文集 第51回(ハードウェア), 9-10, 1995-09-20

    IPSJ 

  • Preliminary Evaluation of Cache Configurations for Multithreaded Architecture  [in Japanese]

    浦田 卓治 , 中村 宏 , 朴 泰祐 , 中澤 喜三郎

    近年、プロセッサの処理速度と主記憶アクセスレーテンシのギャップがプロセッサの実効性能に与える影響は、極めて大きくなっている。このためにキャッシュメモリが用いられ、プログラムの制御フローが予測可能な場合には、プリフェッチなどの手段でメモリアクセスレーテンシを隠蔽することが可能である。しかし、一般にプログラム制御フローが予測不能な場合には、キャッシュミス時のメモリアクセスレーテンシは隠蔽できない。そこ …

    全国大会講演論文集 第51回(ハードウェア), 5-6, 1995-09-20

    IPSJ 

  • NAS Parallel Benchmarks Evaluation on CP-PACS Pilot-Model  [in Japanese]

    HATTORI Masaki , ITAKURA Ken'ichi , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    In this paper, we evaluate the total performance of the prototype of CP-PACS named PILOT-1 by actual measurement. CP-PACS, a massively parallel processor is aimed to solve large scale scientific probl …

    IPSJ SIG Notes 57, 43-48, 1995-08-24

    References (5) Cited by (1)

  • A Network Performance Evaluation Simulator Generation System INSPIRE for Massively Parallel Processing  [in Japanese]

    HARADA Tomoki , SONE Takeshi , BOKU Taisuke , NAKAMURA Hiroshi , NAKAZAWA Kisaburo

    In this paper, we propose general purpose network simulator generation system named INSPIRE. In this system, a user can describe various characteristics of the network, for instance, network resources …

    IPSJ SIG Notes 113, 65-72, 1995-08-23

    References (6) Cited by (10)

  • Advanced Techniques for Performance Improvement of Hyper - Crossbar Network  [in Japanese]

    BOKU Taisuke , SONE Takeshi , MISHIMA Takeshi , ITAKURA Ken'ichi , NAKAZAWA Kisaburo , NAKAMURA Hiroshi

    Hyper-Crossbar Network has several excellent features as an inter-PU network of massively parallel processing systems. In researches on this network so far, the routing algorithm is based on store-and …

    IPSJ Journal 36(7), 1610-1618, 1995-07-15

    IPSJ  IR  References (6) Cited by (4)

  • Theoretical Performance Analysis of Throughput of Hyper-Crossbar Network  [in Japanese]

    山根 幸治 , 三島 健 , 朴 泰祐 , 中村 宏 , 中澤 喜三郎

    超並列計算機向きのプロセッサ間結合ネットワークの一つであるハイパクロスバ・ネットワーク(HXB)は、特にランダム転送において、他のネットワークに比べて高いスループットを実現できることが知られている。これまでHXBに於けるランダム転送性能は、主に計算機シミュレーションによって評価されてきた。また、理論解析によるHXBの転送性能は、メッセージのブロックを無視した確率モデルによってのみ評価されている。そ …

    全国大会講演論文集 第50回(ハードウェア), 31-32, 1995-03-15

    IPSJ 

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