米田 尚弘 YONEDA Takahiro

ID:9000004752738

広島大学工学部 Faculty of Engineering, Hiroshima University (1997年 CiNii収録論文より)

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Articles:  1-7 of 7

  • A PWM Signal Multiply-Accumulate Circuit using a Charge Packet Counting Technique  [in Japanese]

    NOMASAKI Daisuke , YONEDA Takahiro , NAGATA Makoto , IWATA Atsushi

    As for a multiply-accumulation (MAC) of parallel PWM signals based on the switched current integration technique, its operation scale is limited by the range of linear integration voltage. A 0.8umCMOS …

    Technical report of IEICE. ICD 97(230), 17-24, 1997-08-22

    References (5) Cited by (6)

  • A Minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques  [in Japanese]

    NAGATA Makoto , YONEDA Takahiro , NOMASAKI Daisuke , SANO Makoto , IWATA Atsushi

    A CMOS Minimum Distance Search Circuit based on Analog-Digital merged architecture is implemented with 0.8μm CMOS technology. 8bit 8-dimensional PWM vectors are expressed in 4bit sub-PWM pulses. Dista …

    Technical report of IEICE. ICD 97(25), 57-64, 1997-04-25

    References (7) Cited by (4)

  • A Minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques  [in Japanese]

    Nagata Makoto , Yoneda Takahiro , Nomasaki Daisuke , Sano Makoto , Iwata Atsushi

    A CMOS Minimum Distance Search Circuit based on Analog-Digital merged architecture is implemented with 0.8μm CMOS technology. 8bit 8-dimensional PWM vectors are expressed in 4bit sub-PWM pulses. Dista …

    Technical report of IEICE. FTS 97(29), 57-64, 1997-04-25

  • A Minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques  [in Japanese]

    NAGATA Makoto , YONEDA Takahiro , NOMASAKI Daisuke , SANO Makoto , IWATA Atsushi

    A CMOS Minimum Distance Search Circuit based on Analog-Digital merged architecture is implemented with 0.8μm CMOS technology. 8bit 8-dimensional PWM vectors are expressed in 4bit sub-PWM pulses. Dista …

    IEICE technical report. Computer systems 97(27), 57-64, 1997-04-25

    References (7)

  • Analog to Pulse Density Converter  [in Japanese]

    Yoneda Takahiro , Nagata Makoto , Iwata Atsushi

    素子の微細化に伴い電源電圧が低下すると、電流モードが電圧モードと比較して広い入力ダイナミックレンジを持つことができるためアナログ処理に有利となる。今回、電流モードのアナログ信号をパルス密度(PDM)に変換する回路(APDC)を考案した。入力電流値に比例したパルス密度が得られる。また、その変換精度を向上する回路方式についても検討したので報告する。

    Proceedings of the IEICE General Conference 1996年.エレクトロニクス(2), 203, 1996-03-11

  • Pulse Width Modulation based signal processing circuits and its application for Kohonen Network  [in Japanese]

    NAGATA Makoto , YONEDA Takahiro , IWATA Atsushi

    This paper describes basic operational circuits for analog-digital merged circuit architecture using pulse width modulation signals. A PWM multi-functional circuit and a new PWM signal processing circ …

    IEICE technical report. Computer systems 95(20), 71-78, 1995-04-27

    References (3) Cited by (6)

  • CMOS Adder Circuit for Pulse Width Modulation Signals  [in Japanese]

    Yoneda Takahiro , Iwata Atsushi

    パルス幅変調信号(PWM)を用いたアナログ信号とディジタル信号を融合させた信号処理回路を提案する。PWM信号は2値のパルスであるが、パルス幅にアナログの情報を持っているので、PWM信号を積分することによりアナログ信号に変換できる。今回、この性質を利用して多数のPWM信号を加算する回路を検討したので報告する。

    Proceedings of the IEICE General Conference 1995年.エレクトロニクス(2), 220, 1995-03-27

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