Masao Yanagisawa Masao Yanagisawa

Articles:  1-20 of 41

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  • Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures

    Hirokazu Kodera , Masao Yanagisawa , Nozomu Togawa

    A scan-path test is one of the useful design-for-test techniques, in which testers can observe and control registers inside the target LSI chip directly. On the other hand, the risk of side-channel at …

    情報処理学会論文誌 54(7), 2013-07-15

    IPSJ 

  • Integrating Wearable Sensor Technology into Project-management Process

    Koji Ara , Tomoaki Akitomi , Nobuo Sato , Kunio Takahashi , Hideyuki Maeda , Kazuo Yano , Masao Yanagisawa

    A sensor-based project management process, which uses continuous sensing data of face-to-face communication, was developed for integration into current project management processes. To establish a pra …

    情報処理学会論文誌 53(4), 13p, 2012-04-15

    IPSJ 

  • Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint

    SODE TANAKA Mikiko , TOGAWA Nozomu , YANAGISAWA Masao , GOTO Satoshi

    With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capa …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 94(12), 2482-2489, 2011-12-01

    J-STAGE  References (18)

  • Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint

    SODE TANAKA Mikiko , TOGAWA Nozomu , YANAGISAWA Masao , GOTO Satoshi

    With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design tha …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 94(4), 1082-1090, 2011-04-01

    J-STAGE  References (14) Cited by (1)

  • A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit

    Youhei Tsukamoto , Masao Yanagisawa , Tatsuo Ohtsuki , Nozomu Togawa

    Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial prod …

    IPSJ transactions on system LSI design methodology 4, 60-69, 2011-02-08

    IPSJ 

  • Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

    NARA Ryuta , SATOH Kei , YANAGISAWA Masao , OHTSUKI Tatsuo , TOGAWA Nozomu

    Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to protect cryptograph …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 93(12), 2481-2489, 2010-12-01

    J-STAGE  References (30) Cited by (17)

  • A Two-Level Cache Design Space Exploration System for Embedded Applications

    TOJO Nobuaki , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    Recently, two-level cache, L1 cache and L2 cache, is commonly used in a processor. Particularly in an embedded system whereby a single application or a class of applications is repeatedly executed on …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(12), 3238-3247, 2009-12-01

    J-STAGE  References (16) Cited by (5)

  • A Scan-Based Attack Based on Discriminators for AES Cryptosystems

    NARA Ryuta , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    A scan chain is one of the most important testing techniques, but it can be used as side-channel attacks against a cryptography LSI. We focus on scan-based attacks, in which scan chains are targeted f …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(12), 3229-3237, 2009-12-01

    J-STAGE  References (9) Cited by (15)

  • Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

    OHCHI Akira , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. <i>Distributed-register architectures</i> can reduce the influence of intercon …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(12), 3169-3179, 2009-12-01

    J-STAGE  References (15) Cited by (7)

  • X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction

    SHI Youhua , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    This paper presents a novel X-handling technique, which removes the effect of unknowns on compacted test response with maximal compaction ratio. The proposed method combines with the current X-toleran …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(12), 3119-3127, 2009-12-01

    J-STAGE  References (11)

  • Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2^n)

    TANIMURA Kazuyuki , NARA Ryuta , KOHARA Shunitsu , SHI Youhua , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), that is a type of public-key cryptography. Montgomery multiplier is commonly used to compute the …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(9), 2304-2317, 2009-09-01

    J-STAGE  References (19)

  • An L1 Cache Design Space Exploration System for Embedded Applications

    TOJO Nobuaki , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We ca …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(6), 1442-1453, 2009-06-01

    J-STAGE  References (11)

  • A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss

    SHI Youhua , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 91(12), 3514-3523, 2008-12-01

    J-STAGE  References (24)

  • A Secure Test Technique for Pipelined Advanced Encryption Standard

    SHI Youhua , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    In this paper, we presented a Design-for-Secure-Test (DFST) technique for pipelined AES to guarantee both the security and the test quality during testing. Unlike previous works, the proposed method c …

    IEICE Transactions on Information and Systems 91(3), 776-780, 2008-03-01

    J-STAGE  References (12) Cited by (1)

  • Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains

    SHI Youhua , TOGAWA Nozomu , KIMURA Shinji , YANAGISAWA Masao , OHTSUKI Tatsuo

    This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel requ …

    IEICE Trans. Fundamentals, A 89(4), 996-1004, 2006-04-01

    References (31) Cited by (1)

  • A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier

    UCHIDA Jumpei , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem on …

    IEICE transactions on electronics 89(3), 243-249, 2006-03-01

    References (13)

  • A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition

    TOGAWA Nozomu , TACHIKAKE Koichi , MIYAOKA Yuichiro , YANAGISAWA Masao , OHTSUKI Tatsuo

    This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm s …

    IEICE Trans. on Information and Systems, D 88(7), 1340-1349, 2005-07-01

    References (22) Cited by (10)

  • Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis

    KAWAZU Hideki , UCHIDA Jumpei , MIYAOKA Yuichiro , TOGAWA Nozomu , YANAGISAWA Masao , OHTSUKI Tatsuo

    A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b=k×n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not nec …

    IEICE Trans. Fundamentals, A 88(4), 876-884, 2005-04-01

    References (21) Cited by (8)

  • A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction

    SHI Youhua , KIMURA Shinji , YANAGISAWA Masao , OHTSUKI Tatsuo

    Test data volume and power consumption for scan-based designs are two major concerns in system-on-a-chip testing. However, test set compaction by filling the don't-cares will invariably increase the s …

    IEICE transactions on fundamentals of electronics, communications and computer sciences 87(12), 3208-3215, 2004-12-01

    References (28)

  • A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs

    SHI Youhua , KIMURA Shinji , YANAGISAWA Masao , OHTSUKI Tatsuo

    In this paper, we present a test data compression technique to reduce test data volume for multiscan-based designs. In our method the internal scan chains are divided into equal sized groups and two d …

    IEICE transactions on fundamentals of electronics, communications and computer sciences 87(12), 3193-3199, 2004-12-01

    References (27)

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