TAMARU Keikichi

ID:9000004802389

Department of Electronics, Kyoto University (1996年 CiNii収録論文より)

Search authors sharing the same name

Articles:  1-1 of 1

  • A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs

    MOSHNYAGA Vasily G. , TAMARU Keikichi

    As IC fabrication technology enters a deep-submicron region with device feature sizes lt0.35μm, interconnect becomes the most dominant factor in design of high-speed Application Specific Integrated Ci …

    IEICE Trans. Inf. & Syst., D 79(10), 1389-1395, 1996-10-25

    References (24) Cited by (1)

Page Top