TAMARU Keikichi


Department of Electronics, Kyoto University (1996年 CiNii収録論文より)

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  • A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs

    MOSHNYAGA Vasily G. , TAMARU Keikichi

    As IC fabrication technology enters a deep-submicron region with device feature sizes lt0.35μm, interconnect becomes the most dominant factor in design of high-speed Application Specific Integrated Ci …

    IEICE Trans. Inf. & Syst., D 79(10), 1389-1395, 1996-10-25

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