島野 裕樹 SHIMANO Hiroki

ID:9000004974025

立命館大学大学院理工学研究科 Graduate School of Science and Engineering, Ritsumeikan University (2010年 CiNii収録論文より)

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Articles:  1-4 of 4

  • Multi-Function Programmable SOI-Memory MFPM  [in Japanese]

    SHIMANO Hiroki , ARIMOTO Kazutami , FUJINO Takashi

    SoC(System On Chip)に使用されているメモリを機能で分類すると,プログラムやデータの格納領域としての"バッファメモリ",外部データと同じデータが格納されているアドレスを検索する"連想メモリ",に分類することができる.また,外部から入力したデータと,メモリ記憶素子に格納されているデータで演算を行い,演算結果を出力する"ロジックインメモリ"も提案されている.本論文では,SOI-トランジ …

    The IEICE transactions on information and systems 93(6), 931-948, 2010-06-01

    References (18)

  • A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform  [in Japanese]

    SHIMANO Hiroki , MORISHITA Fukashi , DOSAKA Katsumi , ARIMOTO Kazutami

    The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of thi …

    IEICE technical report 107(1), 41-46, 2007-04-05

    References (8)

  • A 1V 46ns 16Mbit SOI-DRAM with Body Control Technique  [in Japanese]

    SHIMOMURA Ken'ichi , SHIMANO Hiroki , SAKASHITA Narumi , OKUDA Fumihiro , OASHI Toshiyuki , YAMAGUCHI Yasuo , ARIMOTO Kazutami , KOMORI Shinji , KYUMA Kazuo

    This paper describes key design techniques in a 16Mbit SOI-DRAM which has achieved 46ns RAS access time at 1V power supply by utilizing transistor operation mode transition. SOI devices are inherently …

    Technical report of IEICE. ICD 97(56), 31-36, 1997-05-22

    References (8)

  • A 1.6G Byte/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture  [in Japanese]

    SAKASHITA Narumi , NITTA Yasuhiko , OKUDA Fumihiro , SHIMOMURA Ken'ichi , SHIMANO Hiroki , TSUKUDE Masaki , ARIMOTO Kazutami , BABA Shinji , KOMORI Shinji , KYUMA Kazuo , ABE Haruhiko

    This paper describes key techniques for a 1.6G Byte/s high bandwidth 1Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory sys …

    Technical report of IEICE. ICD 96(64), 53-58, 1996-05-23

    References (12)

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