ICHIKAWA Tetsuya

ID:9000016259819

Kamakura Office, Mitsubishi Electric Engineering Company Limited (2007年 CiNii収録論文より)

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Articles:  1-2 of 2

  • Leakage Analysis of DPA Countermeasures at the Logic Level

    SAEKI Minoru , SUZUKI Daisuke , ICHIKAWA Tetsuya

    In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally …

    IEICE Trans. Fundamentals, A 90(1), 169-178, 2007-01-01

    References (21) Cited by (1)

  • Random Switching Logic : A New Countermeasure against DPA and Second-Order DPA at the Logic Level

    SUZUKI Daisuke , SAEKI Minoru , ICHIKAWA Tetsuya

    This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each …

    IEICE TRANS. FUNDAMENTALS, A 90(1), 160-168, 2007-01-01

    DOI  References (16) Cited by (10)

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