有本 和民 ARIMOTO Kazutami

ID:9000246815695

岡山県立大学情報工学部 Faculty of Computer Science and System Engineering, Okayama Prefectural University (2014年 CiNii収録論文より)

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Articles:  1-20 of 80

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  • An asynchronous serial multiplier for digital fearing aid  [in Japanese]

    KONDO Masafumi , OKAMOTO Daichi , SATO Yoichiro , YOKOGAWA Tomoyuki , ARIMOTO Kazutami

    Recently, digital hearing aids with digital signal processor (DSP) become widely used because of increasing of hearing impaired people caused by population aging. The high functionality of a digital h …

    IEICE technical report. Circuits and systems 114(312), 11-16, 2014-11-20

  • An asynchronous serial multiplier for digital fearing aid  [in Japanese]

    KONDO Masafumi , OKAMOTO Daichi , SATO Yoichiro , YOKOGAWA Tomoyuki , ARIMOTO Kazutami

    Recently, digital hearing aids with digital signal processor (DSP) become widely used because of increasing of hearing impaired people caused by population aging. The high functionality of a digital h …

    Mathematical Systems Science and its Applications : IEICE technical report 114(313), 11-16, 2014-11-20

  • An asynchronous serial multiplier for digital fearing aid  [in Japanese]

    Masafumi Kondo , Tomoyuki Yokogawa , Yoichiro Sato , Kazutami Arimoto , 有本 和民

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus architecture for GALS systems. However, since only the shared bus type architectu …

    研究報告アルゴリズム(AL) 2014-AL-150(3), 1-6, 2014-11-13

    IPSJ  IPSJ 

  • A distributed asynchronous arbiter for ring segmented bus type GALS systems  [in Japanese]

    ODAGIRI Yoshiki , AKARI Masaki , KONDO Masafumi , YOKOGAWA Tomoyuki , SATO Yoichiro , ARIMOTO Kazutami

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) …

    Technical report of IEICE. VLD 114(123), 237-242, 2014-07-09

  • A distributed asynchronous arbiter for ring segmented bus type GALS systems  [in Japanese]

    ODAGIRI Yoshiki , AKARI Masaki , KONDO Masafumi , YOKOGAWA Tomoyuki , SATO Yoichiro , ARIMOTO Kazutami

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) …

    IEICE technical report. Circuits and systems 114(122), 237-242, 2014-07-09

  • A distributed asynchronous arbiter for ring segmented bus type GALS systems  [in Japanese]

    ODAGIRI Yoshiki , AKARI Masaki , KONDO Masafumi , YOKOGAWA Tomoyuki , SATO Yoichiro , ARIMOTO Kazutami

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) …

    Mathematical Systems Science and its Applications : IEICE technical report 114(125), 237-242, 2014-07-09

  • A distributed asynchronous arbiter for ring segmented bus type GALS systems  [in Japanese]

    ODAGIRI Yoshiki , AKARI Masaki , KONDO Masafumi , YOKOGAWA Tomoyuki , SATO Yoichiro , ARIMOTO Kazutami

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) …

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114(126), 237-242, 2014-07-09

  • A distributed asynchronous arbiter for ring segmented bus type GALS systems  [in Japanese]

    ODAGIRI Yoshiki , AKARI Masaki , KONDO Masafumi , YOKOGAWA Tomoyuki , SATO Yoichiro , ARIMOTO Kazutami

    A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. However, the scalability of RSB is particularly poor, because a global arbiter (GArb) …

    IEICE technical report. Signal processing 114(124), 237-242, 2014-07-09

  • High-speed Petri Net Simulation Using Matrix Compression and GPGPU  [in Japanese]

    KAWAMURA Takashi , SATO Yoichiro , YOKOGAWA Tomoyuki , KONDO Masafumi , ARIMOTO Kazutami

    We proposed a method of evaluating performance of large scale digital systems by modeling with the STPN and executing petri net simulations. In this method, however, it takes very much time to execute …

    IEICE technical report. Communication systems 113(465), 91-96, 2014-03-06

  • High-speed Petri Net Simulation Using Matrix Compression and GPGPU  [in Japanese]

    KAWAMURA Takashi , SATO Yoichiro , YOKOGAWA Tomoyuki , KONDO Masafumi , ARIMOTO Kazutami

    We proposed a method of evaluating performance of large scale digital systems by modeling with the STPN and executing petri net simulations. In this method, however, it takes very much time to execute …

    IEICE technical report. Circuits and systems 113(463), 91-96, 2014-03-06

  • High-speed Petri Net Simulation Using Matrix Compression and GPGPU  [in Japanese]

    KAWAMURA Takashi , SATO Yoichiro , YOKOGAWA Tomoyuki , KONDO Masafumi , ARIMOTO Kazutami

    We proposed a method of evaluating performance of large scale digital systems by modeling with the STPN and executing petri net simulations. In this method, however, it takes very much time to execute …

    IEICE technical report. Signal processing 113(464), 91-96, 2014-03-06

  • A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design  [in Japanese]

    YOKOGAWA Tomoyuki , HIGASHIYAMA Daichi , KONDO Masafumi , SATO Yoichiro , ARIMOTO Kazutami

    In this paper, we show a case study where a design of 8bit microcomputer M8R, which is described by Verilog-HDL, is verified using symbolic model checker NuSMV. We provide a framework for translating …

    Technical report of IEICE. VLD 113(454), 177-182, 2014-03-03

  • Modeling Smartphone Apps Using State Machine Diagrams  [in Japanese]

    OCHIMIZU Kyosuke , YOKOGAWA Tomoyuki , MIYAZAKI Hisashi , SATO Yoichiro , ARIMOTO Kazutami

    In this paper, we propose a method for modeling smartphone apps using UML state machine diagrams. We focused on a tap event which is one of user operations on smartphone apps. In our method, changes o …

    Technical report of IEICE. KBSE 113(160), 49-54, 2013-07-25

  • Modeling Smartphone Apps Using State Machine Diagrams  [in Japanese]

    OCHIMIZU Kyosuke , YOKOGAWA Tomoyuki , MIYAZAKI Hisashi , SATO Yoichiro , ARIMOTO Kazutami

    In this paper, we propose a method for modeling smartphone apps using UML state machine diagrams. We focused on a tap event which is one of user operations on smartphone apps. In our method, changes o …

    Technical report of IEICE. SS 113(159), 49-54, 2013-07-25

  • AT-2-4 Outline of Massively Parallel Embedded Processor "MX" and its applications  [in Japanese]

    Arimoto Kazutami , Noda Hideyuki

    組み込み機器におけるメディア処理アクセラレーションを実現するため,弊社ではSoC(System on Chip)組み込み向けIPである超並列プロセッサコア(MX)を開発している。本報告では高いプログラマビリティ、演算性能およびエネルギー効率を両立するMXプロセッサのハードウェアアーキテクチャ概要を紹介する。またソフトウェア開発を支援する開発環境およびこれを用いて実際に開発を行ったアプリケーション事 …

    Proceedings of the IEICE General Conference 2010年_基礎・境界, "SS-29"-"SS-32", 2010-03-02

  • Communicator Chip for Power-aware, Dependable, and High-performance Communication Link Using PCI Express: PEACH  [in Japanese]

    HANAWA TOSHIHIRO , BOKU TAISUKE , MIURA SHIN'ICHI , SATO MITSUHISA , ARIMOTO KAZUTAMI

    我々は,組込みシステムに適したディペンダブル省電力高性能通信機構として,PCI Express を用いた通信リンク PEARL を提案している.本論文では PEARL を実現するためのコミュニケータチップ,PEACH チップの概要,機能について述べる.PEACH チップは,4 レーンの PCI Express Gen2 を 4 ポート持ち,4 コアの M32R プロセッサ,DMA コントローラを内 …

    研究報告計算機アーキテクチャ(ARC) 2010-ARC-187(12), 1-6, 2010-01-21

    IPSJ  References (14)

  • Communicator Chip for Power-aware, Dependable, and High-performance Communication Link Using PCI Express: PEACH  [in Japanese]

    HANAWA TOSHIHIRO , BOKU TAISUKE , MIURA SHIN'ICHI , SATO MITSUHISA , ARIMOTO KAZUTAMI

    我々は,組込みシステムに適したディペンダブル省電力高性能通信機構として,PCI Express を用いた通信リンク PEARL を提案している.本論文では PEARL を実現するためのコミュニケータチップ,PEACH チップの概要,機能について述べる.PEACH チップは,4 レーンの PCI Express Gen2 を 4 ポート持ち,4 コアの M32R プロセッサ,DMA コントローラを内 …

    研究報告組込みシステム(EMB) 2010-EMB-15(12), 1-6, 2010-01-21

    IPSJ  References (14)

  • Application of Massively Parallel Embedded Processor MX to Image Processing and Image Recognition  [in Japanese]

    NAKAJIMA Masami , KONDO Hiroyuki , ARIMOTO Kazutami

    The Journal of the Institute of Image Information and Television Engineers 63(9), 1193-1195, 2009-09-01

    References (8)

  • Application of the massively parallel embedded processor (MX) to real-time image processing  [in Japanese]

    YAMASAKI Hiroyuki , SUGIMURA Takeaki , NODA Hideyuki , YAMAMOTO Osamu , OKUNO Yoshihiro , ARIMOTO Kazutami

    We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an accelarator for the multimedia processing. It realizes both high flexibilities and h …

    IEICE technical report 108(86), 33-38, 2008-06-13

  • C-12-32 Implementation of AES Processing on Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1  [in Japanese]

    Tagami M. , Kumaki T. , Imai Y. , Koide T. , Mattausch H.J. , Ishizaki M. , Gyohten T. , Noda H. , Okuno Y. , Arimoto K.

    Proceedings of the Society Conference of IEICE C-12-32, 101, 2008

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