Studies on top-down and bottom-up design methodologies of CMOS LSI employing bit-mapping CAD system ビットマップCADシステムを用いたトップ・ダウン及びボトム・アップCMOS LSI設計手法に関する研究

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Author

    • Pham Cong kha ファム コン カー

Bibliographic Information

Title

Studies on top-down and bottom-up design methodologies of CMOS LSI employing bit-mapping CAD system

Other Title

ビットマップCADシステムを用いたトップ・ダウン及びボトム・アップCMOS LSI設計手法に関する研究

Author

Pham Cong kha

Author(Another name)

ファム コン カー

University

上智大学

Types of degree

工学博士

Grant ID

甲第117号

Degree year

1992-03-31

Note and Description

博士論文

Table of Contents

  1. Contents / p1 (0004.jp2)
  2. 1 Introduction / p1 (0006.jp2)
  3. 1.1 Background / p2 (0007.jp2)
  4. 1.2 Scope of the Dissertation / p3 (0007.jp2)
  5. 2 A Bitmap Memory Bank of Region Access / p9 (0010.jp2)
  6. 2.1 Introduction / p10 (0011.jp2)
  7. 2.2 The System Employing Bitmap Memory Bank / p11 (0011.jp2)
  8. 2.3 Hardware Configuration / p13 (0012.jp2)
  9. 2.4 Software Configuration / p15 (0013.jp2)
  10. 2.5 Special Purpose LSI Chips of Bitmap Memory Bank / p16 (0014.jp2)
  11. 2.6 Evaluation of Bitmap Memory Bank / p18 (0015.jp2)
  12. 2.7 Future Works / p20 (0016.jp2)
  13. 2.8 Conclusion / p21 (0016.jp2)
  14. 3 A CMOS Cell Compiler for a Bit-Mapping CAD System / p35 (0023.jp2)
  15. 3.1 Introduction / p36 (0024.jp2)
  16. 3.2 Outline of Bit-mapping CAD / p38 (0025.jp2)
  17. 3.3 CMOS Cell Compiler(CCC) / p39 (0025.jp2)
  18. 3.4 Application Example and Discussion / p44 (0028.jp2)
  19. 3.5 Conclusion / p45 (0028.jp2)
  20. 4 BITDRC:A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System / p67 (0039.jp2)
  21. 4.1 Introduction / p68 (0040.jp2)
  22. 4.2 DRC Program for a Bit-mapping CAD System / p71 (0041.jp2)
  23. 4.3 BITDRC / p73 (0042.jp2)
  24. 4.4 Results and Discussion / p79 (0045.jp2)
  25. 4.5 Conclusion / p81 (0046.jp2)
  26. 5 A Small Analog-to-Digital Converter Employing an Analog-Digital-Balance Circuit / p99 (0055.jp2)
  27. 5.1 Introduction / p100 (0056.jp2)
  28. 5.2 Analog-Digital-Balance Circuit and Analysis / p100 (0056.jp2)
  29. 5.3 4-bit A/D Converter / p104 (0058.jp2)
  30. 5.4 Conclusion / p106 (0059.jp2)
  31. 6 Concluding Remarks / p123 (0067.jp2)
  32. Acknowledgments / p127 (0069.jp2)
  33. List of Pubplications / p129 (0070.jp2)
7access

Codes

  • NII Article ID (NAID)
    500000083611
  • NII Author ID (NRID)
    • 8000000083821
  • DOI(NDL)
  • Text Lang
    • eng
  • NDLBibID
    • 000000247925
  • Source
    • Institutional Repository
    • NDL ONLINE
    • NDL Digital Collections

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