Design of optimized high performance interconnect schemes for ULSI devices ULSIのための高性能多層配線技術に関する研究

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Author

    • Minakakshisundaran B.Anand ミナクシスンダラン バラスブラマニアン アナンド

Bibliographic Information

Title

Design of optimized high performance interconnect schemes for ULSI devices

Other Title

ULSIのための高性能多層配線技術に関する研究

Author

Minakakshisundaran B.Anand

Author(Another name)

ミナクシスンダラン バラスブラマニアン アナンド

University

早稲田大学

Types of degree

博士(工学)

Grant ID

乙第1439号

Degree year

1999-03-04

Note and Description

博士論文

Table of Contents

  1. CONTENTS / p1 (0005.jp2)
  2. Acknowledgement / p3 (0006.jp2)
  3. Chapter1 INTRODUCTION / p1 (0007.jp2)
  4. 1.1 Impact of interconnects / p2 (0008.jp2)
  5. 1.2 Necessity of optimizing interconnect parameters / p6 (0010.jp2)
  6. 1.3 Outline of thesis / p9 (0011.jp2)
  7. References / p11 (0012.jp2)
  8. Chapter2 METHODOLOGY FOR OPTIMIZING INTERCONNECT PARAMETERS / p13 (0013.jp2)
  9. 2.1 Overview of optimization method / p16 (0015.jp2)
  10. 2.2 Building a system-level model / p20 (0017.jp2)
  11. 2.3 Verifying the validity of the model / p36 (0025.jp2)
  12. 2.4 Manipulation of model to facilitate optimization / p38 (0026.jp2)
  13. 2.5 Impact of assumptions on generality of results / p40 (0027.jp2)
  14. 2.6 Summary / p43 (0028.jp2)
  15. References / p44 (0029.jp2)
  16. Chapter3 DERIVATION OF OPTIMIZED INTERCONNECT TECHNOLOGY ROADMAP / p47 (0030.jp2)
  17. 3.1 Baseline optimization / p48 (0031.jp2)
  18. 3.2 Effects of constraints / p57 (0035.jp2)
  19. 3.3 Optimum interconnect parameter roadmap / p70 (0042.jp2)
  20. 3.4 Impact of wiresizing on results / p72 (0043.jp2)
  21. References / p74 (0044.jp2)
  22. Chapter4 DEMONSTRATION OF FEASIBILITY OF A GAS-DIELECTRIC PROCESS / p77 (0045.jp2)
  23. 4.1 Proposed process flow / p79 (0046.jp2)
  24. 4.2 Demonstration of feasibility / p82 (0048.jp2)
  25. 4.3 Requirements of the bridge layer / p88 (0051.jp2)
  26. 4.4 Summary / p104 (0059.jp2)
  27. References / p105 (0059.jp2)
  28. Chapter5 INVESTIGATION OF INTEGRATION ISSUES IN GAS-DIELECTRIC PROCESS / p107 (0060.jp2)
  29. 5.1 Background for wire temperature problem / p109 (0061.jp2)
  30. 5.2 Derivation of estimates of power dissipation in wires / p111 (0062.jp2)
  31. 5.3 Wire temperature simulation details / p124 (0069.jp2)
  32. 5.4 Results of wire temperature simulation / p126 (0070.jp2)
  33. 5.5 Bridge layer sag / p137 (0075.jp2)
  34. 5.6 Free-standing interconnect structure / p142 (0078.jp2)
  35. 5.7 Summary / p152 (0083.jp2)
  36. References / p153 (0083.jp2)
  37. Chapter6 DEVELOPMENT OF LOW RESISTANCE INTERCONNECTS / p155 (0084.jp2)
  38. 6.1 Low resistance aluminum reflow process / p156 (0085.jp2)
  39. 6.2 Integration issues in the dual damascene process / p162 (0088.jp2)
  40. 6.3 Proposed elevated stopper process / p165 (0089.jp2)
  41. 6.4 Integration results of the elevated stopper process / p171 (0092.jp2)
  42. 6.5 Summary / p177 (0095.jp2)
  43. References / p178 (0096.jp2)
  44. Chapter7 CONCLUSION / p179 (0096.jp2)
  45. 研究業績 / p185 (0099.jp2)
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Codes

  • NII Article ID (NAID)
    500000173714
  • NII Author ID (NRID)
    • 8000000173990
  • DOI(NDL)
  • NDLBibID
    • 000000338028
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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