Design of optimized high performance interconnect schemes for ULSI devices ULSIのための高性能多層配線技術に関する研究
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著者
書誌事項
- タイトル
-
Design of optimized high performance interconnect schemes for ULSI devices
- タイトル別名
-
ULSIのための高性能多層配線技術に関する研究
- 著者名
-
Minakakshisundaran B.Anand
- 著者別名
-
ミナクシスンダラン バラスブラマニアン アナンド
- 学位授与大学
-
早稲田大学
- 取得学位
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博士(工学)
- 学位授与番号
-
乙第1439号
- 学位授与年月日
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1999-03-04
注記・抄録
博士論文
目次
- CONTENTS / p1 (0005.jp2)
- Acknowledgement / p3 (0006.jp2)
- Chapter1 INTRODUCTION / p1 (0007.jp2)
- 1.1 Impact of interconnects / p2 (0008.jp2)
- 1.2 Necessity of optimizing interconnect parameters / p6 (0010.jp2)
- 1.3 Outline of thesis / p9 (0011.jp2)
- References / p11 (0012.jp2)
- Chapter2 METHODOLOGY FOR OPTIMIZING INTERCONNECT PARAMETERS / p13 (0013.jp2)
- 2.1 Overview of optimization method / p16 (0015.jp2)
- 2.2 Building a system-level model / p20 (0017.jp2)
- 2.3 Verifying the validity of the model / p36 (0025.jp2)
- 2.4 Manipulation of model to facilitate optimization / p38 (0026.jp2)
- 2.5 Impact of assumptions on generality of results / p40 (0027.jp2)
- 2.6 Summary / p43 (0028.jp2)
- References / p44 (0029.jp2)
- Chapter3 DERIVATION OF OPTIMIZED INTERCONNECT TECHNOLOGY ROADMAP / p47 (0030.jp2)
- 3.1 Baseline optimization / p48 (0031.jp2)
- 3.2 Effects of constraints / p57 (0035.jp2)
- 3.3 Optimum interconnect parameter roadmap / p70 (0042.jp2)
- 3.4 Impact of wiresizing on results / p72 (0043.jp2)
- References / p74 (0044.jp2)
- Chapter4 DEMONSTRATION OF FEASIBILITY OF A GAS-DIELECTRIC PROCESS / p77 (0045.jp2)
- 4.1 Proposed process flow / p79 (0046.jp2)
- 4.2 Demonstration of feasibility / p82 (0048.jp2)
- 4.3 Requirements of the bridge layer / p88 (0051.jp2)
- 4.4 Summary / p104 (0059.jp2)
- References / p105 (0059.jp2)
- Chapter5 INVESTIGATION OF INTEGRATION ISSUES IN GAS-DIELECTRIC PROCESS / p107 (0060.jp2)
- 5.1 Background for wire temperature problem / p109 (0061.jp2)
- 5.2 Derivation of estimates of power dissipation in wires / p111 (0062.jp2)
- 5.3 Wire temperature simulation details / p124 (0069.jp2)
- 5.4 Results of wire temperature simulation / p126 (0070.jp2)
- 5.5 Bridge layer sag / p137 (0075.jp2)
- 5.6 Free-standing interconnect structure / p142 (0078.jp2)
- 5.7 Summary / p152 (0083.jp2)
- References / p153 (0083.jp2)
- Chapter6 DEVELOPMENT OF LOW RESISTANCE INTERCONNECTS / p155 (0084.jp2)
- 6.1 Low resistance aluminum reflow process / p156 (0085.jp2)
- 6.2 Integration issues in the dual damascene process / p162 (0088.jp2)
- 6.3 Proposed elevated stopper process / p165 (0089.jp2)
- 6.4 Integration results of the elevated stopper process / p171 (0092.jp2)
- 6.5 Summary / p177 (0095.jp2)
- References / p178 (0096.jp2)
- Chapter7 CONCLUSION / p179 (0096.jp2)
- 研究業績 / p185 (0099.jp2)
