Reduced instruction set computer architectures for VLSI

著者

• Katevenis, Manolis G. H.

書誌事項

Reduced instruction set computer architectures for VLSI

Manolis G.H. Katevenis

（ACM doctoral dissertation awards, 1984）

MIT Press, c1985

注記

Originally presented as author's thesis (Ph.D.)--University of California, Berkeley, 1983

Bibliography: p. [201]-207

Includes index

詳細情報

• NII書誌ID(NCID): BA00032190
• ISBN:
  • 0262111039
• LCCN: 85000078
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Cambridge, Mass.
• ページ数/冊数: 215 p.
• 大きさ: 24 cm
• 分類:
  • LCC : QA76.9.A73
  • DC19 : 621.3819/5835
• 件名:
  • LCSH : Computer architecture
  • LCSH : Integrated circuits -- Very large scale integration
• 親書誌ID:
  • BA00032215