Reconfigurable processor-array : a bit-sliced parallel computer
著者
書誌事項
Reconfigurable processor-array : a bit-sliced parallel computer
（Research monographs in parallel and distributed computing）
Pitman , MIT Press, 1989
- : pbk.
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注記
Bibliography: p151-160
内容説明・目次
- 巻冊次
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: pbk. ISBN 9780262680578
内容説明
Processor arrays have established themselves as an inexpensive form of parallel computer suitable for a wide range of highly parallel applications. They achieve their performance by huge replication of simple processors known as processing elements or PE. This book investigates enhancements to the conventional bit serial PE with the aim of improving its performance in situations where the small grain parallelism of a single instruction-stream, multiple data stream (SIMD) class parallel computer architecture is inefficient.The book describes the development of an SIMD class parallel computer based on processor arrays. Surprisingly, for many problems a large array of bit serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism.The implementation of the architecture as a chip design, for possible VLSI realization, is described, and an appendix contains a high level formal description of the processing element in a registertransfer language.Andrew Rushton teaches at the University of Southampton. "Reconfigurable Processor Array" is included in the series Research Monographs in Parallel and Distributed Computing, copublished with Pitman Publishing.
- 巻冊次
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ISBN 9780273087991
内容説明
A description of the development of a parallel computer of the single instruction-stream, multiple data-stream (SIMD) class. It is a type of SIMD computer known as a processor-array and the computer described here is known as the reconfigurable processor-array or RPA. For simple operations a large array of bit-serial processing elements is a better source of processing power than a small array of complex processors, and the RPA described here is enhanced with floating-point, multiplication and data cache facilities to improve the operation of such arrays. The RPA also has features which allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip deisgn, for possible VLSI realization, is described, and the appendix contains a high-level formal description of the processing element in a register-transfer language.
目次
- Part 1 Introduction to parallel computers: a brief history of parllel computers
- types of parallel computer - the Flynn classification
- why choose a processor-array? - SIMD versus MIMD
- applications of processor-arrays - meteorology and oceanography, earth resources, medical, engineering design, signal processing, artificial intelligence
- a case study of two SIMD networks - the distributed-array-processor (DAP), the connection machine. Part 2 Architecture of the reconfigurable processor-array: system description - overview of the RPA system
- adaptive parallelism and reconfigurability - architecture of the bit-slice PE
- data storage in the array
- conditional operations
- floating-point enhancements - mantissa alignment
- a description of the RPA PE - instruction and ALU control field, external RAM port and host interface
- RPA performance estimates. Part 3 Implementation of the RPA processor chip: choice of technology and design rules
- design methodology - clocking scheme, layout of 16 PE chip, layout of 1 PE chip, gate matrix layout
- design of the PE components
- chip packaging. Part 4 Conclusions. Appendix: A register of transfer description of the PE and chip - the specification language and description of the PE and chip.
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