VLSI 91 : proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991
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Bibliographic Information
VLSI 91 : proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991
（IFIP transactions, A . Computer science and technology ; 1）
North-Holland, 1992
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Description and Table of Contents
Description
"The major problem in VLSI is really the control of complexity. The hardest part is the control of autonomous yet interacting processes. We do not yet have satisfactory techniques for handling that sort of thing, but I think the techniques we need to develop are independent of whether you are programming or designing the chip." Sidney Michaelson, Initiator of the IFIP Working Group on VLSI. This proceedings, dedicated to the late Prof. Sidney Michaelson, who ten years ago established this IFIP Working Group, reflects the continuing interest in improving design tools and the wide range of engineering concerns surrounding the effective exploitation of VLSI.
Table of Contents
Arithmetic. A Regularly Structured 54-bit Modified Wallace Tree Multiplier (T. Sato et al.). OCAPI: A Circuit for On-line radix 2 High Precision Arithmetic (A. Guyot, Y. Kusumpautri). Digital Signal Processing. The Design of a Highly Pipelined 2nd Order IIR Filter Chip (O.C. McNally, J.V. McCanny, R.F. Woods). Design of a Fully Parallel Viterbi Decoder (J. Sparso, S. Pedersen, E. Paaske). Pipelined BIT-Serial SYNthesis of Digital Filtering ALgorithms (R. Nagalla, L.E. Turner). Formal Methods. Symbolic Model Checking with Partitioned Transition Relations (J.R. Burch, E.M. Clarke, D.E. Long). Integration of Formal Methods with System Design (E.M. Mayger, M.P. Fourman). Deriving Bit-Serial Circuits in Ruby (G. Jones, M. Sheeran). Structuring Hardware Proofs (K. Schneider, R. Kumar, T. Kropf). Physical Design. DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities (K. Doll, F.M. Johannes, G. Sigl). A Flow-Oriented Approach to the Placement of Boolean Networks (S. Mayrhofer, M. Pedram, U. Lauther). Bounds on Net Delays for Physical Design of Fast Circuits (H. Youssef, R.-B. Lin, E. Shragowitz). Area Minimisation of IC Power/Ground Nets by Topology Optimisation (K-H. Erhard, F.M. Johannes). Simulation. On Distributed Logic Simulation using Time Warp (H. Bauer, C. Sporrer, T.H. Krodel). An Integrated Environment for the Design and Simulation of Self-Timed Systems (E.L. Brunvand, M. Starkey). A General Purpose Network Solving System (T.J. Kazmierski et al.). Vision and Neural Architectures. On-Chip CMOS Sensors for VLSI Imaging Systems (P.B. Denyer et al.). A Customizable Neural Processor for Distributed Neural Network Silicon Compiler (J. Quali et al.). A VLSI Module for Analog Adaptive Neural Architectures (D.D. Caviglia, M. Valle, G.M. Bisio). Keynote Paper. Has CAD for VSLI Reached a Dead End? (R. Newton). High-Level Synthesis/ Partitioning-Based Allocation of Dedicated Datapaths in the Architectural Synthesis for High Throughput Applications (W. Geurts et al.). A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment (N. Wehn, J. Biesenack, M. Pilsl). Modelling for Synthesis. Meta VHDL for Higher Level Controller Modelling and Synthesis (A. Jerraya, P.G. Paulin, S. Curry). Towards a Formal Model of VLSI Systems Compatible with VHDL (P.A. Wilsey, T.J. McBrayer and D. Sims). Hardware Design using CASE Tools (W. Glunz, G. Venzl). Processor Design. A VLSI System Design for the Control of High Performance Combustion Engines (A. Laudenbach, M. Glesner, N. Wehn). A Fully Integrated Systolic Spelling Co-Processor (P. Frison, D. Lavenier). Parallel Architecture and VLSI Implementation of a 80 MHz 2D-DCT IDCT Processor (W. Liebsch, K. Boettcher). RT-Level Synthesis. Exact Redundant State Registers Removal Based on Binary Decision Diagrams (B. Lin, A.R. Newton). Resources Restricted Global Scheduling (F.E. Yeung, D.J. Rees). Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays (M.
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