Digital hardware testing : transistor-level fault modeling and testing
著者
書誌事項
Digital hardware testing : transistor-level fault modeling and testing
（The Artech House telecommunication library）
Artech House, c1992
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注記
"Annotated bibliography": p. 303-310
Includes bibliographical references and index
内容説明・目次
内容説明
Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.
目次
- Introduction to digital IC testing
- faults in digital circuits
- bridging faults in random logic
- open faults in random logic
- text generation and fault simulation
- problems
- testing of structured designs (programmable logic arrays)
- testing of random access memory
- testing of sequential circuits
- microprocessor testing
- design for testability
- current testing
- reliability testing.
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