Logic synthesis and optimization
著者
書誌事項
Logic synthesis and optimization
（The Kluwer international series in engineering and computer science, VLSI,
Kluwer Academic Publishers, c1993
大学図書館所蔵 件 / 全31件
-
該当する所蔵館はありません
- すべての絞り込み条件を解除する
注記
Papers from the International Symposium on Logic Synthesis and Microprocessor Architecture, held in Iizuka, Japan, in July 1992
Includes bibliographical references and index
内容説明・目次
内容説明
Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.
目次
Preface. 1. A New Exact Minimizer for Two-Level Logic Synthesis. 2. A New Graph Based Prime Computation Technique. 3. Logic Synthesizers, the Transduction Method and Its Extension, SYLON. 4. Network Optimization Using Don't-Cares and Boolean Relations. 5. Multi-Level Logic Minimization of Large Combinatorial Circuits by Partitioning. 6. A Partitioning Method for Area Optimization by Tree Analysis. 7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams. 8. Delay Models and Exact Timing Analysis. 9. Challenges to Dependable Asynchronous Processor Design. 10. Efficient Spectral Techniques for Logic Synthesis. 11. FPGA Design by Generalized Functional Decomposition. 12. Logic Synthesis with EXOR Gates. 13. AND-EXOR Expressions and Their Optimization. 14. A Generation Method for EXOR-Sum-of-Products Expressions Using Shared Binary Decision Diagrams. 15. A New Technology Mapping Method Based on Concurrent Factorization and Mapping. 16. Gate Sizing for Cell-Based Designs. Subject Index.
「Nielsen BookData」 より