Algorithms for synthesis and testing of asynchronous circuits
著者
書誌事項
Algorithms for synthesis and testing of asynchronous circuits
（The Kluwer international series in engineering and computer science, SECS 232 . VLSI,
Kluwer Academic, c1993
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注記
Includes bibliographical references (p. 309-320) and index
内容説明・目次
内容説明
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
目次
List of Figures. List of Tables. List of Theorems and Procedures. Preface. 1: Introduction. 2: Overview of the Design Methodology. 3: Previous Work. 4: The Signal Transition Graph Model. 5: The State Encoding Methdology. 6: The Synthesis Methodology. 7: The Design for Testability Methodology. 8: Conclusions. Subject Index.
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