Bibliographic Information

Logic synthesis

Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer

(Computer engineering series)

McGraw-Hill, c1994

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Note

Includes bibliographical references and index

Description and Table of Contents

Description

Logic synthesis enables VSLI designers to rapidly lay out the millions of transistors and interconnecting wires that form the circuitry on modern chips, without having to plot each individual logic circuit. This guide to logic synthesis techniques spotlights not only the synthesis of two-level, multi-level and combinational circuits, but also their testability.

Table of Contents

Introduction.Translation from HDL Descriptions.Two-Level Combinatorial Circuits.Synthesis of Two-Level Circuits.Testability of Two-Level Circuits.Multilevel Combinational Circuits.Synthesis of Multilevel Circuits.Delay of Multilevel Circuits.Testability of Multilevel Circuits.Ongoing Work and Future Directions.

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