Parallel architectures and compilation techniques : proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Canada, 24-26 August, 1994

著者

• IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
• Cosnard, M. (Michel)
• Gao, Guang R.
• Silberman, Gabriel M.

書誌事項

Parallel architectures and compilation techniques : proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '94, Montréal, Canada, 24-26 August, 1994

edited by Michel Cosnard, Guang R. Gao, Gabriel M. Silberman

（IFIP transactions, A . Computer science and technology ; 50）

North-Holland, 1994

内容説明・目次

内容説明

Fine and medium grain parallelism continues to hold its own as a vital, vibrant research topic. Within the area, new developments in superscalar and VLIW architectures and their associated compilation techniques, have provided exciting new avenues to extract performances from a slowing technology curve. Comprising 28 full-length papers and a number of short (poster) papers, this publication offers a high quality exploration of the current state-of-the art in the field. It should be of particular interest to those involved in control structures and microprogramming; processor architectures; computer systems implementation; programming techniques; and software engineering.

目次

• Part 1 High-performance architectures: EM-C - programming with explicit parallelism and locality for EM-4 multiprocessor, M. Sato et al
• a fine-grain threaded abstract machine, J. Vasell
• tradeoffs in the design of single chip multiprocessors, D.H. Albonesi and I. Koren. Part 2 Code generation for multithreaded and dataflow architectures: an evaluation of optimized threaded code generation, L. Roh et al
• functional I-structure and M-structure implementations of NAS Benchmark FT, S. Sur and A.P.W. Bohm
• the plan-do style compilation technique for eager data transfer in thread-based execution, M. Yasugi et al. Part 3 Memory and cache issues: a compiler-assisted scheme for adaptive cache coherence enforcement, T.N. Nguyen et al
• the impact of cache coherence protocols on systems using fine-grain data synchronization, D.B. Glasco et al
• towards a programming environment for a computer with intelligent memory, A. Asthana et al. Part 4 Distributed memory machines: communication analysis for multicomputer compilers, I. Kim and M. Wolfe
• automatic data layout using 0-1 integer programming, R. Bixby et al
• processor tagged descriptors - a data structure for compiling for distributed-memory multicomputers, E. Su et al. Part 5 Multi-level parallelism: resource spackling - a framework for integrating register allocation in local and global schedulers, D.A. Berson et al
• an approach to combine predicted/speculative execution for programs with unpredictable branches, M. Srinivas et al
• a PDG-based tool and its use in analyzing program control dependences, C.I. Newburn et al. Part 6 Compiling for parallel machines: static analysis of barrier synchronization in explicitly parallel programs, T.E. Jeremiassen and S.J. Eggers
• exploiting the parallelism exposed by partial evaluation, R. Surati and A.A. Berlin
• effects of loop fusion and statement migration on the speedup of vector multiprocessors, M. Al-Mouhamed and L. Bic. Part 7 Logic languages: practical static mode analysis of concurrent logic languages, E. Tick
• demand-driven dataflow for concurrent committed-choice code, B. Massey and E. Tick
• exploitation of fine-grain parallelism in logic languages on massively parallel architectures, H. Kim and J.-L. Gaudiot. Part 8 Application specific architectures: from SIGNAL to fine-grain parallel implementations, O. Maffeis and P. Le Guernic
• microcode generation for flexible parallel target architectures, R. Leupers et al
• a fleng compiler for PIE64, H. Nakada et al. Part 9 Functional languages, dataflow models and implementation: compiling higher-order functions for tagged-dataflow, R. Rondogiannis and W.W. Wadge
• dataflow-based lenient implementation of a functional language, valid, on conventional multi-processors, S. Kusakabe et al
• dataflow and logicflow models for defining a parallel prolog abstract machine, P. Kacsuk
• towards a computational model for UFO, J. Sargeant et al. (Part Contents).

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詳細情報

• NII書誌ID(NCID): BA23060049
• ISBN:
  • 0444819266
• 出版国コード: ne
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: Amsterdam
• ページ数/冊数: xii, 362 p.
• 大きさ: 23 cm
• 親書誌ID:
  • BA13962399