Quick-turnaround ASIC design in VHDL : core-based behavioral synthesis

Author(s)

• Romdhane, Mohamed S. Ben
• Madisetti, V. (Vijay)
• Hines, John W.

Bibliographic Information

Quick-turnaround ASIC design in VHDL : core-based behavioral synthesis

Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

（The Kluwer international series in engineering and computer science, SECS 367 . VLSI, computer architecture, and digital signal processing）

Kluwer Academic Publishers, c1996

Note

Includes bibliographical references (p. 171-177) and index

Details

• NCID: BA28733533
• ISBN:
  • 0792397444
• LCCN: 96019108
• Country Code: us
• Title Language Code: eng
• Text Language Code: und
• Place of Publication: Boston
• Pages/Volumes: xviii, 180 p.
• Size: 25 cm
• Classification:
  • LCC : TK7874.6
  • DC20 : 621.382/2/0285
• Subject Headings:
  • LCSH : Application specific integrated circuits -- Design -- Data processing
  • LCSH : VHDL (Computer hardware description language)
  • LCSH : Computer-aided design
• Parent Bibliography ID:
  • BA0004729X