The Verilog hardware description language
著者
書誌事項
The Verilog hardware description language
Kluwer Academic Publishers, c1998
4th ed
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注記
Includes index
内容説明・目次
内容説明
This is a revised edition of a standard text, which presents the language through examples illustrating the important styles of representation, including: structural models, behavioural models of combinational and sequential circuits for logic synthesis, FSM-datapath models, and cycle-accurate descriptions. A chapter on behavioural synthesis presents the use of cycle-accurate descriptions with these tools. This text can be used as a useful resource for engineers and students interested in describing, simulating, and synthesizing digital systems. The order of coverage of representation styles matches typical introductory courses (structural, synthesizable, FSM-datapath, cycle-accurate). An appendix with a tutorial workbook style is keyed into the introduction. For architecture courses, modelling of simple pipelined processors is presented. The pack includes a CD-ROM containing the VeriwellTM Verilog simulator, the Synplicity TM Synplify TM FPGA synthesis software, examples from the book in text and PDF format, and lecture slides in PDF format. Usage of the synthesis tool is time-limited; directions for obtaining an extended licence are provided.
The simulator and synthesis tools are available for several platforms.
目次
- Verilog - a tutorial introduction
- behavioural modelling
- concurrent processes
- logic level modelling
- advanced timing
- logic synthesis
- behavioural synthesis
- user-defined primitives
- switch level modelling
- projects. Appendices: tutorial questions and discussion
- lexical conventions
- Verilog operators
- Verilog gate types
- registers, memories, integers, and time
- system tasks and functions
- formal syntax definition.
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