Modern VLSI design : system-on-chip design/ Wayne Wolf
著者
書誌事項
Modern VLSI design : system-on-chip design/ Wayne Wolf
（Modern semiconductor design series）
Prentice Hall PTR, c2002
3rd ed
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内容説明・目次
内容説明
Modern VLSI Design, System-on-Chip Design, Third Edition is a comprehensive, "bottom-up" guide to the entire VLSI design process, focusing on the latest solutions for system-on-chip design. Wayne Wolf reviews every aspect of digital design, from planning and layout to fabrication and packaging -- adding up-to-the-minute coverage of key trends every practitioner must understand, from the latest HDLs to IP-based design.KEY TOPICS:Modern VLSI Design, System-on-Chip Design, Third Edition has been updated to reflect today's unprecedented requirements for chips that deliver high performance and low power. Wolf presents extensive new coverage of chip device interconnects designed to solve delay bottlenecks. He introduces advanced low-power design techniques that improve reliability and extend battery life in portable consumer electronics, covering power issues at every level of abstraction, from circuits to architecture. This edition contains significantly enhanced coverage of hardware description languages, including detailed introductions to both Verilog and HDL. Wolf also presents new guidance for architecting both IP-based and embedded processors.MARKET:For all electrical engineers involved with (or planning to become involved with) VLSI design.
目次
Preface to the Third Edition.
Preface to the Second Edition.
Preface.
1. Digital Systems and VLSI.
Why Design Integrated Circuits? Integrated Circuit Manufacturing. CMOS Technology. Integrated Circuit Design Techniques. A Look into the Future. Summary. References. Problems.
2. Transistors and Layout.
Introduction. Fabrication Processes. Transistors. Wires and Vias. Design Rules. Layout Design and Tools. References. Problems.
3. Logic Gates.
Introduction. Combinational Logic Functions. Static Complementary Gates. Switch Logic. Alternative Gate Circuits. Low-Power Gates. Delay Through Resistive Interconnect. Delay Through Inductive Interconnect. References. Problems.
4. Combinational Logic Networks.
Introduction. Standard Cell-Based Layout. Simulation. Combinational Network Delay. Logic and Interconnect Design. Power Optimization. Switch Logic Networks. Combinational Logic Testing. References. Problems.
5. Sequential Machines.
Introduction. Latches and Flip-Flops. Sequential Systems and Clocking Disciplines. Sequential System Design. Power Optimization. Design Validation. Sequential Testing. References. Problems.
6. Subsystem Design.
Introduction. Subsystem Design Principles. Combinational Shifters. Adders. ALUs. Multipliers. High-Density Memory. Field-Programmable Gate Arrays. Programmable Logic Arrays. References. Problems.
7. Floorplanning.
Introduction. Floorplanning Methods. Off-Chip Connections. References. Problems.
8. Architecture Design.
Introduction. Hardware Description Languages. Register-Transfer Design. High-Level Synthesis. Architectures for Low Power. Systems-on-Chips and Embedded CPUs. Architecture Testing. References. Problems.
9. Chip Design.
Introduction. Design Methodologies. Kitchen Timer Chip. Microprocessor Data Path. References. Problems.
10. CAD Systems and Algorithms.
Introduction. CAD Systems. Switch-Level Simulation. Layout Synthesis. Layout Analysis. Timing Analysis and Optimization. Logic Synthesis. Test Generation. Sequential Machine Optimizations. Scheduling and Binding. Hardware/Software Co-Design. References. Problems.
Appendix A: A Chip Designer's Lexicon.
Appendix B: Chip Design Projects.
Class Project Ideas. Project Proposal and Specification. Design Plan. Design Checkpoints and Documentation.
Appendix C: Kitchen Timer Model.
Hardware Modeling in C.
Index.
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