Computer architecture : a quantitative approach
Author(s)
Bibliographic Information
Computer architecture : a quantitative approach
Morgan Kaufmann Publishers, 2003
3rd ed
- : cloth
Available at / 43 libraries
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Note
Includes bibliographical references and index
Description and Table of Contents
Description
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing. The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others.
In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together. The authors present a new organization of the material as well, reducing the overlap with their other text, "Computer Organization and Design: A Hardware/Software Approach 2/e", and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies. Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom. Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.
It presents state-of-the-art design examples including: IA-64 architecture and its first implementation, the Itanium; Pipeline designs for Pentium III and Pentium IV; The cluster that runs the Google search engine; EMC storage systems and their performance; Sony Playstation 2; Infiniband, a new storage area and system area network; SunFire 6800 multiprocessor server and its processor the UltraSPARC III; and Trimedia TM32 media processor and the Transmeta Crusoe processor. It examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market. It updates all the examples and figures with the most recent benchmarks, such as SPEC 2000. It expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors. It analyzes capacity, cost, and performance of disks over two decades. It surveys the role of clusters in scientific computing and commercial computing. It presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
It presents detailed descriptions of the design of storage systems and of clusters. It surveys memory hierarchies in modern microprocessors and the key parameters of modern disks. It presents a glossary of networking terms.
Table of Contents
Foreword Preface Acknowledgments Chapter 1 - Fundamentals of Computer Design Chapter 2 - Instruction Set Principles and Examples Chapter 3 - Instruction-Level Parallelism and Its Dynamic Exploitation Chapter 4 - Exploiting Instruction-Level Parallelism with Software Approaches Chapter 5 - Memory Hierarchy Design Chapter 6 - Multiprocessors and Thread-Level Parallelism Chapter 7 - Storage Systems Chapter 8 - Interconnection Networks and Clusters Appendix A - Pipelining: Basic and Intermediate Concepts Appendix B - Solutions to Selected Exercises Online Appendices Appendix C - A Survey of RISC Architectures for Desktop, Server, and Embedded Computers Appendix D - An Alternative to RISC: The Intel 80x86 Appendix E - Another Alternative to RISC: The VAX Architecture Appendix F - The IBM 360/370 Architecture for Mainframe Computers Appendix G - Vector Processors Revised by Krste Asanovic Appendix H - Computer Arithmetic by David Goldberg Appendix I - Implementing Coherence Protocols References Index
by "Nielsen BookData"
