Verification by error modeling : using testing techniques in hardware verification

著者

    • Radecka, Katarzyna
    • Zilic, Zeljko

書誌事項

Verification by error modeling : using testing techniques in hardware verification

by Katarzyna Radecka, Zeljko Zilic

(Frontiers in electronic testing, 25)

Kluwer Academic, c2003

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注記

Includes bibliographical references (p. [197]-209) and index

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