ASIC and FPGA verification : a guide to component modeling

著者

書誌事項

ASIC and FPGA verification : a guide to component modeling

Richard Munden

（The Morgan Kaufmann series in systems on silicon / Peter J. Ashenden, Wayne Wolf, series editors）

Elsevier/Morgan Kaufmann, c2005

  • : pbk
  • : hdk

タイトル別名

ASIC & FPGA verification

大学図書館所蔵 件 / 全6件

この図書・雑誌をさがす

注記

Includes index

内容説明・目次

内容説明

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

目次

  • 1.Introduction to Board-Level Verification
  • 2.Tour of a simple model
  • 3.VHDL packages for component models
  • 4.Introduction to SDF
  • 5.Anatomy of a VITAL Model
  • 6.Modeling Delays
  • 7.VITAL truth tables
  • 8.Modeling timing constraints
  • 9.Modeling registered devices
  • 10.Conditional delays and timing constraints
  • 11.Negative timing constraints
  • 12.Timing Files and Backannotation
  • 13.Adding Timing to Your RTL Code
  • 14.Modeling Memories
  • 15.Considerations for Component Modeling
  • 16.Modeling Component Centric Features
  • 17.Testbenches for Component Models

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