Verification methodology manual for SystemVerilog

著者

• Bergeron, Janick

書誌事項

Verification methodology manual for SystemVerilog

by Janick Bergeron ... [et al.]

Springer, 2006

注記

Includes bibliographical references and index

内容説明・目次

内容説明

Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

目次

Verification Planning.- Assertions.- Testbench Infrastructure.- Stimulus and Response.- Coverage-Driven Verification.- Assertions for Formal Tools.- System-Level Verification.- Processor Integration Verification.

「Nielsen BookData」 より

詳細情報

• NII書誌ID(NCID): BA74622441
• ISBN:
  • 0387255389
• LCCN: 2005051724
• 出版国コード: us
• タイトル言語コード: eng
• 本文言語コード: eng
• 出版地: New York
• ページ数/冊数: xvii, 503 p.
• 大きさ: 25 cm
• 分類:
  • LCC : TK7885.7
  • DC22 : 621.39/2
• 件名:
  • LCSH : Verilog (Computer hardware description language)
  • LCSH : Integrated circuits -- Verification