Routing Congestion in VLSI Circuits : Estimation and Optimization

著者

書誌事項

Routing Congestion in VLSI Circuits : Estimation and Optimization

Prashant Saxena, Rupesh S. Shelar , Sachin S. Sapatnekar

Springer, c2007

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内容説明・目次

内容説明

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

目次

The Origins of Congestion.- An Introduction to Routing Congestion.- The Estimation of Congestion.- Placement-level Metrics for Routing Congestion.- Synthesis-level Metrics for Routing Congestion.- The Optimization of Congestion.- Congestion Optimization During Interconnect Synthesis and Routing.- Congestion Optimization During Placement.- Congestion Optimization During Technology Mapping and Logic Synthesis.- Congestion Implications of High Level Design.

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詳細情報

  • NII書誌ID(NCID)
    BA82021742
  • ISBN
    • 9780387300375
  • 出版国コード
    us
  • タイトル言語コード
    eng
  • 本文言語コード
    eng
  • 出版地
    New York
  • ページ数/冊数
    xiv, 248 p.
  • 大きさ
    25 cm
  • 分類
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