Defect-oriented testing for nano-metric CMOS VLSI circuits
Author(s)
Bibliographic Information
Defect-oriented testing for nano-metric CMOS VLSI circuits
（Frontiers in electronic testing, 34）
Springer, c2007
2nd ed.
Available at 3 libraries
Note
Includes bibliographical references and index
Description and Table of Contents
Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Table of Contents
Functional and Parametric Defect Models.- Digital CMOS Fault Modeling.- Defects in Logic Circuits and their Test Implications.- Testing Defects and Parametric Variations in RAMs.- Defect-Oriented Analog Testing.- Yield Engineering.- Conclusion.
by "Nielsen BookData"