System-on-chip test architectures : nanometer design for testability

著者

    • Wang, Laung-Terng
    • Stroud, Charles E.
    • Touba, Nur

書誌事項

System-on-chip test architectures : nanometer design for testability

edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

（The Morgan Kaufmann series in systems on silicon / Peter J. Ashenden, Wayne Wolf, series editors）

Morgan Kaufmann Pub., c2008

大学図書館所蔵 件 / 全9件

この図書・雑誌をさがす

注記

Includes bibliographical references and index

内容説明・目次

内容説明

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

目次

  • Introduction
  • Digital Test Architectures
  • Fault-Tolerant Design
  • SOC/NOC Test Architectures
  • SIP Test Architectures
  • Delay Testing
  • Low-Power Testing
  • Coping with Physical Failures, Soft Errors, and Reliability Issues
  • Design for Manufacturability and Yield
  • Design for Debug and Diagnosis
  • Software-Based Self-Testing
  • FPGA Testing
  • MEMS Testing
  • High-Speed I/O Interface
  • Analog and Mixed-Signal Test Architectures
  • RF Testing
  • Testing Aspects of Nanotechnology Trends.

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