System-on-chip test architectures : nanometer design for testability
Author(s)
Bibliographic Information
System-on-chip test architectures : nanometer design for testability
（The Morgan Kaufmann series in systems on silicon / Peter J. Ashenden, Wayne Wolf, series editors）
Morgan Kaufmann Pub., c2008
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Note
Includes bibliographical references and index
Description and Table of Contents
Description
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Table of Contents
- Introduction
- Digital Test Architectures
- Fault-Tolerant Design
- SOC/NOC Test Architectures
- SIP Test Architectures
- Delay Testing
- Low-Power Testing
- Coping with Physical Failures, Soft Errors, and Reliability Issues
- Design for Manufacturability and Yield
- Design for Debug and Diagnosis
- Software-Based Self-Testing
- FPGA Testing
- MEMS Testing
- High-Speed I/O Interface
- Analog and Mixed-Signal Test Architectures
- RF Testing
- Testing Aspects of Nanotechnology Trends.
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