CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
著者
書誌事項
CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
（Frontiers in electronic testing, 40）
Springer, c2008
大学図書館所蔵 全5件
注記
Includes bibliographical references (p. 183-189) and index
内容説明・目次
内容説明
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
目次
Foreword. Preface. Acronyms. 1. INTRODUCTION AND MOTIVATION. 1.1 Motivation. 1.2 SRAM in the Computer Memory Hierarchy. 1.3 Technology Scaling and SRAM Design and Test. 1.4 SRAM test economics. 1.5 SRAM Design and Test Tradeoffs. 1.6 Redundancy. 2. SRAM CIRCUIT DESIGN AND OPERATION. 2.1 Introduction. 2.2 SRAM block structure. 2.3 SRAM cell design. 2.4 Cell layout considerations. 2.5 Sense Amplifier and Bit Line Precharge-Equalization. 2.6 Write Driver. 2.7 Row Address Decoder and Column MUX. 2.8 Address Transition Detector. 2.9 Timing Control Schemes. 2.10 Summary. 3. SRAM CELL STABILITY: DEFINITION, MODELING AND TESTING. 3.1 Introduction. 3.2 Static noise margin of SRAM cells. 3.3 SNM Definitions. 3.4 Analytical expressions for SNM calculations. 3.5 SRAM cell stability sensitivity factors. 3.6 SRAM cell stability fault model. 3.7 SRAM Cell Stability Detection Concept. 3.8 March tests and stability fault detection in SRAMs. 3.9 Summary. 4. TRADITIONAL SRAM FAULT MODELS AND TEST PRACTICES. 4.1 Introduction. 4.2 Traditional fault models. 4.3 Traditional SRAM test practices. 4.4 Summary. 5. TECHNIQUES FOR DETECTION OF SRAM CELLS WITH STABILITY FAULTS. 5.1 Introduction. 5.2 Classification of SRAM cell stability test techniques. 5.3 Passive SRAM Cell Stability Test Techniques. 5.4 Active SRAM Cell Stability Test Techniques. 5.5 Summary. 6. SOFT ERROR IN SRAMs: SOURCES, MECHANISM AND MITIGATION TECHNIQUES. 6.1 Introduction. 6.2 Soft Error Mechanism. 6.3 Sources of Soft Errors. 6.4 Soft Errors and Defects in the Pull-Up Path of a Cell. 6.5 Soft Error Mitigation Techniques. 6.6 Leakage-Reduction Techniques and the SER. 6.7 Summary. References. Index.
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