Computer architecture : a quantitative approach
Author(s)
Bibliographic Information
Computer architecture : a quantitative approach
Morgan Kaufmann Pub., an imprint of Elsevier, c2012
5th ed
Available at / 40 libraries
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University Library for Agricultural and Life Sciences, The University of Tokyo図
007.6S:H52:5th ed5010820461
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Note
Includes bibliographical references and index
Description and Table of Contents
Description
Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book, which became a part of Intel's 2012 recommended reading list for developers, covers the revolution of mobile computing. It also highlights the two most important factors in architecture today: parallelism and memory hierarchy.
This fully updated edition is comprised of six chapters that follow a consistent framework: explanation of the ideas in each chapter; a crosscutting issues section, which presents how the concepts covered in one chapter connect with those given in other chapters; a putting it all together section that links these concepts by discussing how they are applied in real machine; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. Formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability are included. The book also covers virtual machines, SRAM and DRAM technologies, and new material on Flash memory. Other topics include the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, vector architectures, multicore processors, and warehouse-scale computers (WSCs). There are updated case studies and completely new exercises. Additional reference appendices are available online.
This book will be a valuable reference for computer architects, programmers, application developers, compiler and system software developers, computer system designers and application developers.
Table of Contents
Printed TextChap 1: Fundamentals of Quantitative Design and AnalysisChap 2: Memory Hierarchy DesignChap 3: Instruction-Level Parallelism and Its ExploitationChap 4: Data-Level Parallelism in Vector, SIMD, and GPU ArchitecturesChap 5: Multiprocessors and Thread-Level ParallelismChap 6: The Warehouse-Scale ComputerApp A: Instruction Set PrinciplesApp B: Review of Memory HierarchyApp C: Pipelining: Basic and Intermediate Concepts
OnlineApp D: Storage SystemsApp E: Embedded SystemsApp F: Interconnection NetworksApp G: Vector ProcessorsApp H: Hardware and Software for VLIW and EPICApp I: Large-Scale Multiprocessors and Scientific ApplicationsApp J: Computer Arithmetic App K: Survey of Instruction Set ArchitecturesApp L: Historical Perspectives
by "Nielsen BookData"
