SOC (system-on-a-chip) testing for plug and play test automation
Author(s)
Bibliographic Information
SOC (system-on-a-chip) testing for plug and play test automation
（Frontiers in electronic testing, v. 21）
Springer Science+Business Media, c2002
- : pbk.
Available at 1 libraries
Note
Originally published by Kluwer academic publishers in 2002
Reprinted from a special issue of the "Journal of electronic testing (JETTA) volume18, Nos.4&5"
Volume No. from back cover
Description and Table of Contents
Description
System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity.
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing.
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.
Table of Contents
Overview.- On IEEE P1500's Standard for Embedded Core Test.- Test Planning, Access and Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- On Concurrent Test of Core-Based SOC Design.- A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm.- The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.- CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.- An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.- Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.- Test Data Compression.- Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.- Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.- Interconnect, Crosstalk and Signal Integrity.- Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.- Signal Integrity: Fault Modeling and Testing in High-Speed SoCs.- On-Chip Clock Faults' Detector.
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