Shared memory multiprocessing
Author(s)
Bibliographic Information
Shared memory multiprocessing
MIT Press, c1992
Available at 15 libraries
Note
Includes bibliographical references
Description and Table of Contents
Description
This book is the first to provide a coherent review of current research in shared memory multiprocessing in the United States and Japan. Shared memory multiprocessors are becoming the dominant architecture for small-scale parallel computation. This book is the first to provide a coherent review of current research in shared memory multiprocessing in the United States and Japan. It focuses particularly on scalable architectures that will be able to support hundreds of microprocessors as well as on efficient and economical ways of connecting these fast microprocessors. The twenty contributions are divided into sections covering the experience to date with multiprocessors, cache coherency, software systems, and examples of scalable shared memory multiprocessors.Norihisa Suzuki is Director of the IBM Tokyo Research Laboratory. He is the co-inventor of the snoop cache, which in the early 1980s helped make it possible to build affordable and reliable shared memory multiprocessors.
Table of Contents
- Part 1 Experience: experience with the Firefly multiprocessor workstation, Susan Owiski
- design and evaluation of snoop-cache-based multiprocessor, TOP-1, Shigenori Shimizu, et al
- symbolic computation algorithms on shared memory multiprocessors, E.M. Clarke, et al
- experimental evaluation of algorithmic performance on two shared memory multiprocessors, Anand Sivasubramaniam, et al. Part 2 Cache coherency: formal verification of the Gigamax cache consistency protocol, Kenneth McMillan and James Schwalbe
- an evaluation of cache coherence protocols for multiprocessors, Sandra Johnson Baylor, et al
- KRPP - the Kyushu University reconfigurable parallel processor - cache architecture and cache coherence schemes, Kazuaki Murakami, et al. Part 3 Software system: MUSTARD - a multiprocessor UNIX for embedded real-time systems, Shuichi Hiroya, et al
- an empirical investigation of the effectiveness and limitations of automatic parallelization, Jaswinder Pal Singh and John L. Hennessy
- fine-grain loop scheduling for MIMD machines, Carrie J. Brownhill, et al
- restructuring a parallel simulator to improve cache behaviour, David R. Cheriton, et al
- a replay mechanism for mostly functional parallel programmes, Robert H. Hastead, Jr and David A. Kranz
- abstracting data-representation and partitioning-scheduling in parallel programmes, Gail A. Alverson and David Notkin. Part 4 Scalable shared memory multiprocessor: latency tolerance through multithreading in large-scale multiprocessors, Kiyoshi Kurihara, et al
- Cenju - a multiprocessor system with a distributed shared memory scheme for modular circuit simulation, Toshiyuki Nakata, et al
- overview and status of the Stanford DASH multiprocessor, Daniel Lenoski, et al
- an analysis of shared-memory synchronization mechanisms, Philip J. Woest and James R. Goodman
- a cache coherence mechanism for scalable, shared-memory multiprocessors, Steven Scott
- dynamic pointer allocation for scalable cache coherence directors, Richard Simoni and Mark Horowitz
- fault-tolerant design for multistage routing networks, Andre DeHon, et al.
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