Reasoning in Boolean networks : logic synthesis and verification using testing techniques
著者
書誌事項
Reasoning in Boolean networks : logic synthesis and verification using testing techniques
（Frontiers in electronic testing, v. 9）
Kluwer Academic, c1997
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注記
Includes bibliographical references and index
内容説明・目次
内容説明
Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques.
While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems.
Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material.
Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies.
目次
Foreword. Preface. 1. Preliminaries. 2. Combinational ATPG. 3. Recursive Learning. 3. And/Or Reasoning Graphs. 5. Logic Optimization. 6. Logic Verification. 7. Conclusions and Future Work. References. Appendix. Index.
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